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atmel-46004a-se-m90e36a-datasheet_052214 features metering features ? metering features fully in compliance with the requirements of iec62052-11, iec62053-22 and iec62053-23, ansi c12.1 and ansi c12.20; applicable in class 0.2s, 0.5s or class 1 poly-phase watt-hour meter or class 2 poly-phase var-hour meter. ? accuracy of 0.1% for active energy and 0.2% for reactive energy over the dynamic range of 6000:1. ? temperature coefficient is 6 ppm/ (typical) for on-chip reference voltage. ? single-point calibration on each phase over the whole dynamic range for active energy; no calibration needed for reactive/apparent energy. ? 1 (typical) temperature sensor accuracy. ? electrical parameters measurement: less than 0.5% fiducial error for vrms, irms, mean active/ reactive/ apparent power, frequency, power factor and phase angle. ? active (forward/reverse), reactive (forwa rd/reverse), apparent energy with indepen- dent energy registers. acti ve/ reactive/ apparent energy can be output by pulse or read through energy registers to adapt to different applications. ? programmable startup and no-load power th reshold, special designed of startup and no-load circuits to eliminate crosstalk among phases achieving better accuracy especially at low power conditions. ? dedicated adc and different gains for phase a/b/c and neutral line current sam- pling circuits. current sampled over current transformer (ct) or rogowski coil (di/dt coil); phase a/b/c voltage sampled over resistor divider network or potential trans- former (pt). ? programmable power modes: normal mode (n mode), idle mode (i mode), detec- tion mode (d mode) and partial measurement mode (m mode). ? fundamental (cf3, 0.2%) and harmonic (cf4, 1%) active energy with dedicated energy and power registers. ? total harmonic distortion (thd) and discret e fourier transform (dft) functions for 2 ~ 32 order harmonic component. thd and dft results available in spi accessible registers. both voltage and current of all phases processed within the same time period. ? event detection: sag, phase loss, reverse voltage/ current phase sequence, reverse flow, calculated neutral line current i nc overcurrent sampled neutral line current i ns overcurrent and thd+n over-threshold. other features ? 3.3v single power supply. operating voltage range: 2.8v~3.6v. metering accuracy guaranteed within 3.0v~3.6v. ? four-wire spi interface with direct memory access (dma) mode to stream out 7- channel adc raw data. ? parameter diagnosis function and programm able interrupt output of the irq inter- atmel m90e36a enhanced poly-phase hi gh-performance wide-span energy metering ic datasheet
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 2 rupt signals and the warnout signal. ? programmable voltage sag detection and zero-crossing output. ? cf1/cf2/cf3/cf4 output active/ reactive/ apparent energy pulses and fundamental/ harmonic energy pulses respectively. ? crystal oscillator frequency : 16.384 mhz. on-chip two capacitors and no need of external capacitors. ? tqfp48 package. ? operating temperature: -40 ~ +85 . application ? poly-phase energy meters of class 0.2s, 0.5s and class 1 which are used in three-phase four-wire (3p4w, y0) or three-phase three-wire (3p3w, y or ) systems. ? data acquisition terminal. ? power monitoring instruments which need to measur e voltage, current, thd, dft, mean power, etc. general description the m90e36a is a poly-phase high performance wide-dynamic range metering ic. the m90e36a incorporates 7 indepen- dent 2nd order sigma-delta adcs, which could be employed in three voltage channels (phase a, b and c) and four current channels (phase a, b, c and neutral line) in a typical three-phase four-wire system. the m90e36a has an embedded dsp which ex ecutes calculation of active energy, reactive energy, apparent energy, fun- damental and harmonic active energy over adc signal and on-chip reference voltage. the dsp also calculates measure- ment parameters such as voltage and current rms va lue as well as mean active/reactive/apparent power. a four-wire spi interface is provided between the m90e36a a nd the external microcontroller. in addition, dma mode can be used for 7-channel adc raw data access, of fering more flexibility in system application. the m90e36a is suitable for poly-phase multi-function meters which could meas ure active/reactive/apparent energy and fundamental/harmonic energy either through four independent energy pulse outputs cf1/cf 2/cf3/cf4 or through the cor- responding registers. with the on-chip thd and dft engine, all phases' thd and dft results can be directly accessed through related regis- ters, thus simplifying hardware desi gn in data acqu isition terminals. the proprietary adc and auto-temperature compensation technology for reference voltage ensure the m90e36a's long- term stability over variat ions in grid and ambien t environment conditions.
3 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 block diagram figure-1 m90e36a block diagram vdd18 regulator temperature sensor current detector adc-v1 adc-v2 adc-v3 adc-i1 adc-i2 adc-i3 adc-in spi interface dsp energy metering (forward/reverse active/reactive/cf generator) measure and monitoring (v/i/rms / sag / phase / frequency) signal analyzer adc sample capture / thd control logic zero crossing cf out power on reset crystal oscillator dma reference voltage vref i1p / i1n v1p / v1n cs sclk sdo sdi osci osco reset cf1 zx0 i2p / i2n i3p / i3n v2p / v2n v3p / v3n i4p / i4n cf2 cf3 cf4 zx1 zx2 power mode configuration pm1 pm0 warnout irq0 irq1 dma_ctrl irq warn out
4 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 features .............. ................. ................ ................ .............. .............. ............... ............. ................... 1 application .............. ................ ................. .............. .............. .............. .............. ............. ................. 2 general description.......... ................ ................. ................ ................. ................ ................ ....... 2 block diagram................. ................. ................ ................ ................. ................ ............... ............. 3 1 pin assignment ....... ................ ................ ................. .............. .............. .............. ............. ........... 8 2 pin description ....... ................ ................ .............. .............. ............... .............. .............. ............ 9 3 function description ........ ................ ................ ................. ................ ................. ............... .. 11 3.1 power supply ............................................................................................................... ....................................11 3.2 clock ...................................................................................................................... .............................................11 3.3 reset ......... ................ ................ ................. ................ ................ ................ ............ ..............................................11 3.3.1 reset pin ..... ................ ................ ................ ................. ................ ............. ............. .................................. 11 3.3.2 power on reset (por) ..................................................................................................... ........................ 11 3.3.3 software reset ........................................................................................................... ............................... 11 3.4 metering function .......................................................................................................... ...............................12 3.4.1 theory of energy register s ............................................................................................... ...................... 12 3.4.2 energy registers ......................................................................................................... .............................. 14 3.4.3 energy pulse output ...................................................................................................... ........................... 14 3.4.4 startup and no-load power ................................................................................................ ...................... 15 3.5 measurement function ....................................................................................................... .........................16 3.5.1 active/ reactive/ apparent power ......................................................................................... .................. 16 3.5.2 fundamental / harmonic active power .......... ............................................................................ ............. 16 3.5.3 mean power factor (pf) . .................................................................................................. ........................ 16 3.5.4 voltage / current rms .................................................................................................... .......................... 16 3.5.5 phase angle .............................................................................................................. ................................. 17 3.5.6 frequency ................................................................................................................ .................................. 17 3.5.7 temperature .............................................................................................................. ................................ 17 3.5.8 thd+n for voltage and current ............................................................................................ ................... 17 3.6 fourier analysis function .................................................................................................. .......................18 3.7 power mode ................................................................................................................. .....................................19 3.7.1 normal mode (n mode) ..................................................................................................... ........................ 19 3.7.2 idle mode (i mode) ....................................................................................................... .............................. 20 3.7.3 detection mode (d mode) .................................................................................................. ....................... 22 3.7.4 partial measurement mode (m mode) ........................................................................................ .............. 23 3.7.5 transition of power modes ...................... .......................................................................... ...................... 24 3.8 event detection ...... ................. ................ ................ ................ ............. ............. ........... ..................................25 3.8.1 zero-crossing dete ction .................................................................................................. ........................ 25 3.8.2 sag detection ............................................................................................................ ................................ 25 3.8.3 phase loss detection ..................................................................................................... .......................... 25 3.8.4 neutral line overcurrent detection ........... ............................................................................ ................. 25 3.8.5 phase sequence erro r detection ........................................................................................... ................. 25 3.9 dc and current rms estimation .............................................................................................. .................25 4 spi / dma interface ......... ................ ................. ................ ................. ................ ............... ....... 26 4.1 interface description ...................................................................................................... ...........................26 4.2 slave mode: spi interface .................................................................................................. ........................27 4.2.1 spi slave interface format ............................................................................................... ........................ 27 4.2.2 reliability enhanc ement feature .......................................................................................... ................... 28 table of contents
5 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 4.3 master mode: dma ........................................................................................................... ...............................28 4.3.1 dma burst transfer for adc sampling ...................................................................................... ............ 28 4.3.2 control sequence for external device ........... .......................................................................... ............... 30 5 calibration method ........ ................. ................ ................ ................. ................ ................. ... 31 5.1 normal mode operation calibration .......................................................................................... ..........31 5.2 partial measurement mode calibration ....................................................................................... ......31 6 register .......... ................. ................ ................ ................. .............. .............. ............. ................ 32 6.1 register list .............................................................................................................. ......................................32 6.2 special registers .. ................. ................ ................ ................ ............. ............. ............. ................................40 6.2.1 soft reset register ...................................................................................................... ............................. 40 6.2.2 irq and warnout signal generation ............. ........................................................................... .............. 40 6.2.3 special configuration regi sters .......................................................................................... .................... 45 6.2.4 last spi data register ................................................................................................... ........................... 48 6.3 low-power modes registers .................................................................................................. ..................49 6.3.1 detection mode registers ................................................................................................. ....................... 49 6.3.2 partial measurement mode re gisters ....................................................................................... .............. 52 6.4 configuration and calibration registers .................................................................................... .....55 6.4.1 start registers and associated checksum operation scheme ........ ................................................... 55 6.4.2 configuration registers .................................................................................................. ......................... 56 6.4.3 energy calibration registers ...................... ....................................................................... ...................... 61 6.4.4 fundamental/harmonic energy calibration registers ........................................................................ ... 63 6.4.5 measurement calibra tion .................................................................................................. ....................... 64 6.5 energy register ............................................................................................................ .................................65 6.5.1 regular energy registers ................................................................................................. ....................... 65 6.5.2 fundamental / harmonic energy register ..... .............................................................................. ........... 67 6.6 measurement registers ...................................................................................................... ........................68 6.6.1 power and power factor registers ......................................................................................... ................ 68 6.6.2 fundamental/ harmonic power and voltage/ current rms registers ................................................. 69 6.6.3 thd+n, frequency, angle and temperature registers ........................................................................ 70 6.7 harmonic fourier analysis registers ........................................................................................ ..........71 7 electrical specification ............ ................. ................ .............. .............. .............. ............. 7 3 7.1 electrical specification ..... ................ ................ ................ ................ ................ .............. .........................73 7.2 metering/ measurement accuracy ............................................................................................. ............75 7.2.1 metering accuracy ........................................................................................................ ............................ 75 7.2.2 measurement accura cy ..................................................................................................... ....................... 76 7.3 interface timing ........................................................................................................... ..................................78 7.3.1 spi interface timing (slave mode) ........................................................................................ .................. 78 7.3.2 dma timing (master mode) ................................................................................................. ..................... 79 7.4 power on reset timing ...... ................. ................ ................ ................ ................ ............... ...........................80 7.5 zero-crossing timing ....................................................................................................... .............................81 7.6 voltage sag and phase loss timing .......................................................................................... .............82 7.7 absolute maximum rating .................................................................................................... ......................83 ordering information ..... ................ ................ .............. .............. ............... .............. ............. ... 84 package dimensions ........... ................ ................. ................ ................. ................ ................ ..... 85 revision history ...... ................. ................ ................ .............. ............... .............. ............ ........... 86
6 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 table-1 pin description ...................................................................................................... ................................................. 9 table-2 power mode mapping ................................................................................................... ....................................... 19 table-3 digital i/o and power pin states in idle mode ........................................................................ ............................. 21 table-4 register list ........................................................................................................ ................................................. 32 table-5 configuration registers .............................................................................................. .......................................... 56 table-6 calibration registers ...................... .......................................................................... ............................................ 61 table-7 fundamental/harmo nic energy calibration registers .................................................................... ..................... 63 table-8 measurement calibration registers ........ ............................................................................ ................................. 64 table-9 regular energy registers ............................................................................................. ....................................... 65 table-10 fundamenta l / harmonic energy register ................ .............................................................. ........................... 67 table-11 power and power factor register ..................................................................................... ................................ 68 table-12 fundamen tal/ harmonic power and voltag e/ current rms registers ...................................................... ........ 69 table-13 thd+n, frequency, angl e and temperature registers ................................................................... ................. 70 table-14 harmonic fourie r analysis results registers ......................................................................... ........................... 71 table-15 measurement pa rameter range and format .............................................................................. ....................... 76 table-16 spi timing specification ............................................................................................ ........................................ 78 table-17 dma timing specification ............................................................................................ ...................................... 79 table-18 power on reset specification ........................................................................................ .................................... 80 table-19 zero-crossing specification ......................................................................................... ...................................... 81 list of tables
7 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 figure-1 m90e36a block diagram ............................................................................................... ....................................... 3 figure-2 pin assignment (top view) ........................................................................................... ........................................ 8 figure-3 energy register oper ation diagram ................................................................................... ................................ 13 figure-4 cfx pulse output regulation .............. ........................................................................... ..................................... 14 figure-5 metering startup handling .................. ......................................................................... ....................................... 15 figure-6 analysis function .......................... ......................................................................... ............................................. 18 figure-7 block diagram in norm al mode ........................................................................................ .................................. 19 figure-8 block diagram in idle mode ............. ............................................................................. ...................................... 20 figure-9 block diagram in dete ction mode ..................................................................................... .................................. 22 figure-10 block diagram in part ial measurement mode .......................................................................... ......................... 23 figure-11 power mode transiti on .............................................................................................. ....................................... 24 figure-12 slave mode ......................................................................................................... .............................................. 26 figure-13 master mode (pin_dir _sel=0) ........................................................................................ ............................... 26 figure-14 read sequence ...................................................................................................... .......................................... 27 figure-15 write sequence ..................................................................................................... ............................................ 27 figure-16 clock mode0 (clk_drv=0, cl k_idle=0) and mode1 (clk_drv=0, clk_idle=1) .................................... 29 figure-17 clock mode2 (clk_drv=1, cl k_idle=0) and mode3 (clk_drv=1, clk_idle=1) .................................... 29 figure-18 sample sequence example ............................................................................................ .................................. 30 figure-19 sample bit sequence example ........................................................................................ ................................. 30 figure-20 irq and warnout generation ........... .............................................................................. .................................. 40 figure-21 current detection regi ster latching scheme ......................................................................... .......................... 49 figure-22 start and checksum regi ster operation scheme ....................................................................... ..................... 55 figure-23 spi timing diagram ................................................................................................. ......................................... 78 figure-24 dma timing diagram ................................................................................................. ....................................... 79 figure-25 power on re set timing (m90e36a and mcu are powered on si multaneously) ............................................. 80 figure-26 power on reset timing in normal & partial measurement mode . ........................................................ ........... 80 figure-27 zero-crossing timing dia gram (per phase) ........................................................................... ........................... 81 figure-28 voltage sag and phase loss timing diagram .......................................................................... ....................... 82 list of figures
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 8 1 pin assignment figure-2 pin assignment (top view) 1 2 3 4 5 6 8 9 10 11 13 25 avdd agnd i1p i1n i2p i2n v1p v1n vref agnd warnout cs test nc dm a_ctrl pm0 sclk cf1 cf2 zx0 irq0 7 12 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 i3p i3n i4p i4n v2p v2n v3p v3n dgnd osci osco zx1 zx2 cf3 cf4 irq1 pm1 sdo sdi reset vdd18 vdd18 dgnd nc nc dgnd dvdd
9 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 2 pin description table-1 pin description name pin no. i/o type description reset 41 i lvttl reset: reset pin (active low) this pin should connect to ground through a 0.1 f filter capacitor and a 10k resistor to vdd. in application it can also directly connect to one out- put pin from microcontroller (mcu). avdd 1 i power avdd: analog power supply this pin provides power supply to the analog part. this pin should connect to dvdd and be decoupled with a 0.1 f capacitor. dvdd 48 i power dvdd: digital power supply this pin provides power supply to t he digital part. it should be decoupled with a 10 f capacitor and a 0.1 f capacitor. vdd18 42, 43 p power vdd18: digital powe r supply (1.8 v) these two pins should be connected together and connected to ground through a 10 f capacitor. dgnd 19, 44, 47 i power dgnd: digital ground agnd 2, 12 i power agnd: analog ground i1p i1n 3 4 i analog i1p: positive input for phase a current i1n: negative inpu t for phase a current these pins are differential inputs for phase a current. note: i1 to phase a and i3 to phase c mapping can be swapped by configur- ing the i1i3swap bit (b13, mmode0) . i2p i2n 5 6 i analog i2p: positive input for phase b current i2n: negative inpu t for phase b current these pins are differential inputs for phase b current. i3p i3n 7 8 i analog i3p: positive input for phase c current i3n: negative inpu t for phase c current these pins are differential inputs for phase c current. note: i1 to phase a and i3 to phase c mapping can be swapped by configur- ing the i1i3swap bit (b13, mmode0) . i4p i4n 9 10 i analog i4p: positive input for n line current i4n: negative input for n line current these pins are differential inputs for n line current. vref 11 o analog vref: output pin for reference voltage this pin should be decoupled with a 10 f capacitor, possibly a 0.1 f ceramic capacitor and a 1nf ceramic capacitor. v1p v1n 13 14 i analog v1p: positive input for phase a voltage v1n: negative input for phase a voltage these pins are differential inputs for phase a voltage. v2p v2n 15 16 i analog v2p: positive input for phase b voltage v2n: negative input for phase b voltage these pins are differential inputs for phase b voltage. v3p v3n 17 18 i analog v3p: positive input for phase c voltage v3n: negative input for phase c voltage these pins are differential inputs for phase c voltage. osci 20 i osc osci: external crystal input osco: external crystal output a 16.384 mhz crystal is connected between osci and osco. there are two on-chip capacitor, therefore no need of external capacitors. osco 21 o osc zx0 zx1 zx2 22 23 24 olvttl zx2/zx1/zx0:zero-crossing output these pins are asserted when voltage or current crosses zero. zero-cross- ing mode can be configured by the zxconfig register (07h).
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 10 cf1 25 o lvttl cf1: (all-phase-sum total) active energy pulse output cf2 26 o lvttl cf2: (all-phase-sum total) reactive/ apparent energy pulse output the output of this pin is determined by the cf2varh bit (b7, mmode0 ) and the cf2esv bit (b8, mmode0 ). cf3 27 o lvttl cf3: (all-phase-sum total) active fundamental energy pulse output cf4 28 o lvttl cf4: (all-phase-sum total) active harmonic energy pulse output warnout 29 o lvttl warnout: fatal error warning this pin is asserted high when there is metering related parameter check- sum error. otherwise this pin stays low. refer to 6.2.2 irq and warnout signal generation . irq0 30 o lvttl irq0: interrupt output 0 this pin is asserted when one or more events in the sysstatus0 register (01h) occur. it is deasserted when there is no bit set in the sysstatus0 register (01h). in detection mode, the irq0 is used to indicate the outpu t of current detec- tor. the irq0 state is cleared when entering or exiting detection mode. irq1 31 o lvttl irq1: interrupt output 1 this pin is asserted when one or more events in the sysstatus1 register (02h) occur. it is deasserted when there is no bit set in the sysstatus1 regis- ter (02h). in detection mode, the irq1 is used to indicate the outpu t of current detec- tor. the irq1 state is cleared when entering or exiting detection mode. pm0 pm1 33 34 ilvttl pm1/0: power mode configuration these two pins define the power mode of m90e36a. refer to ta b l e - 2 . dma_ctrl 36 i lvttl dma_ctrl: dma enable dma is started when this pin is asserted. dma is stopped when this pin is deasserted. refer to 4 spi / dma interface . cs 37 b lvttl cs : chip select (active low) in spi mode, this pin must be driven from high to low for each read/ write operation, and maintain low for the entire operation. in dma mode, this pin is asserted during data transmission. refer to 4 spi / dma interface . sclk 38 b lvttl sclk: serial clock this pin is used as the clock for the spi/dma interface. refer to 4 spi / dma interface . sdo 39 b lvttl sdo: serial data output this pin is used as the data output fo r the spi mode and input for the dma mode. refer to 4 spi / dma interface . sdi 40 b lvttl sdi: serial data input this pin is used as the data input for the spi mode and output for the dma mode. refer to 4 spi / dma interface . test 32 i lvttl this pin should be always connected to dgnd in system application. nc 35, 45, 46 nc: these pins should be left open. table-1 pin description (continued) name pin no. i/o type description
11 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 3 function description 3.1 power supply the m90e36a works with single power rail 3.3v. an on-chip voltage regulator regulates the 1.8v voltage for the digital logic. the regulated 1.8v power is connected to the vdd18 pin. it needs to be bypassed by an external capacitor. the m90e36a has multiple power modes, in idle and detection modes the 1.8v power regulator is not turned on and the digital logic is not powered. when the logic is not powered, al l the configured register values are not kept (all context lost) except for detection mode related registers (10h~13h) for detection mode configuration. user has to re-configure the registers in partial measurement mode or normal mode when transiting from idle or detection mode. refer to 3.7 power mode for power mode details. 3.2 clock the m90e36a has an on-chip oscillator and can directly connect to an external crystal. the osci pin can also be driven with a clock source. the oscillator will be powered down in idle an d detection power modes, as described in 3.7 power mode . 3.3 reset there are three reset sources for the m90e36a: - reset pin - on-chip power on reset circuit - software reset generated by the software reset register 3.3.1 reset pin the reset pin can be asserted to reset the m90e36a. the reset pin has rc filter with typical time constant of 2 s in the i/ o, as well as a 2 s (typical) de-glitch filter. any reset pulse that is shorter than 2 s can not reset the m90e36a. 3.3.2 power on reset (por) the por circuit resets the m90e36a at power up. por circuit triggers reset when: - dvdd power up, crossing the power-up threshold. refer to figure-26 . - vdd18 regulator changing from disable to enable, i.e. from idle or detection mode to partial measurement mode or normal mode. refer to figure-25 . 3.3.3 software reset chip reset can be triggered by writing to the softreset register in normal mode. the software reset is the same as the reset scope generated from the reset pin or por. these three reset sources ha ve the same reset scope. all digital logics and registers, except fo r the harmonic ratio registers will be subject to reset. the harmonic ratio register s can not be reset. ? interface logic: clock dividers ? digital core/ logic: all registers except for the harmonic ratio registers and some other special registers, refer to 6.3.1 detection mode registers .
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 12 3.4 metering function the accumulated energy is converted to pulse frequency on th e cf pins and stored in the corresponding energy registers. the m90e36a provides energy accumulation registers with 0.1 or 0.01 cf resolution. 0.01cf / 0.1cf setting is defined by the 001lsb bit (b9, mmode0 ). 3.4.1 theory of energy registers the energy accumulation runs at 1 mhz clock rate, by accu mulating the power value calculated by the dsp processor. the power accumulation process is equivalent to digitally integrating the instantaneous power with a delta-time of about 1us. the accumulated energy is used to calculate the cf pulses and the corresponding internal energy registers. the accumulated energy is converted to frequency of the cf pulses. one cf usually corresponds to 1kwh / mc (mc is meter constant, e.g. 3200 imp/kwh), and is usually referenced as an energy unit in this datasheet. the internal energy res- olution for accumulation and conversion is 0.01 cf. the 0.01 cf pulse energy constant is referenced as 'pl_constant'. within 0.01 cf, forward and reverse energy are counteracted . when energy exceeds 0.01 pulse, the respective forward/ reverse energy is increased. take the example of active energy, suppose: t0: forward energy register is 12.34 pulses and reverse energy register is 1.23 pulses. from t0 to t1: 0.005 forward pulses appeared. from t1 to t2: 0.004 reverse pulses appeared. from t2 to t3: 0.005 reverse pulses appeared. from t3 to t4: 0.007 reverse pulses appeared. the following table illustrates the proces s of energy accumulation process: when forward/reverse energy reaches 0.1/0.01 pulse, the resp ective register is updated. w hen forward or reverse energy reaches 1 pulse, cfx pins output pulse and the revp/revq bits (b7~0, sysstatus1 ) are updated. refer to figure-3 . t0 t1 t2 t3 t4 input energy + 0.005 -0.004 -0.005 -0.007 bidirectional energy accumulator 0.005 0.001 -0.004 -0.001 forward 0.01 cf 0000 reverse 0.01cf 0001 forward energy register 12.34 12.34 12.34 12.34 12.34 reverse energy register 1.23 1.23 1.23 1.23 1.24
13 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 figure-3 energy register operation diagram for all-phase-sum total of active, reactive and (arithmetic sum) apparent energy, the associated power is obtained by sum- ming the power of the three phases. the accumulation method of all-phase-sum energy is determined by the enpc/enpb/ enpa/absenp/absenq bits (b0~b4, mmode0 ). note that the direction of a ll-phase-sum power and single-phase power might be different. cf gen logic cf pulse bi-directional energy accumulator, roll over positive/negative @ 0.01cf forward energy register accumulator reverse energy register accumulator energy accumulator @ 1mhz (-)0.01 cf (+)0.01 cf + ena abs or arithmetic enb enc phase-a phase-b phase-c power all-phase sum positive cf accumulator negative 0-cf accumulator cf[p/q]revflag forward energy accumulator backward energy accumulator energy accumulator @ 1mhz (-)0.01 cf (+)0.01 cf bi-directional energy accumulator, roll over positive/nega tive @ 0.01cf forward energy accumulator backward energy accumulator energy accumulator @ 1mhz (-)0.01 cf (+)0.01 cf bi-directional energy accumulator, roll over positive/negative @ 0.01cf forward energy register accumulator reverse energy register accumulator energy accumulator @ 1mhz (-)0.01 cf (+)0.01 cf rev[p/q]chg[a/bc} rev[p/q]chgt a/b/c
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 14 3.4.2 energy registers the m90e36a meters non-decomposed total active, reactive and apparent energy, as well as decomposed active funda- mental and harmonic energy. the registers are listed as below. 3.4.2.1 total energy registers each phase and all-phase-sum has the following registers: - active forward/ reverse - reactive forward/ reverse - apparent energy in addition, there is an apparent e nergy all-phase vector sum register. altogether there are 21 energy regist ers. those registers are defined in 6.5.1 regular energy registers . 3.4.2.2 fundamental and harmonic energy registers the m90e36a counts decomposed active fundamental and harmo nic energy. reactive energy is not decomposed to fun- damental and harmonic. the fundamental/harmonic energy is accumulated in the sa me way as active energy accumulation method described above. registers: - fundamental / harmonic - all-phase-sum / phase a / phase b / phase c - forward / reverse altogether there are 16 energy registers. refer to 3.4.2.2 fundamental and harmonic energy registers . 3.4.3 energy pulse output cf1 is fixed to be total active energy output (all-phase-sum). both forward and re verse energy registers can generate the cf pulse (change of forward/ reverse direct ion can generate an interrupt if enabled). cf2 is reactive energy output (all-phase-s um) by default. it can also be configur ed to be arithmetic sum apparent energy output (all-phase-sum) or vector sum apparent energy output (all-phase-sum). cf3 is fixed to be active fundamental energy output (all-phase-sum). cf4 is fixed to be active harmonic energy output (all-phase-sum). figure-4 cfx pulse output regulation for cfx pulse width r egulation, refer to figure-4 . case1 t>=160ms, tp=80ms case 2 10ms<=t<160ms, tp=t/2 case 3 if calculated t < 10ms, force t=10ms, tp=5ms cfx t p =80ms t p =0.5t t 160ms 10ms t<160ms t p =5ms if t<10ms, force t=10ms
15 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 3.4.4 startup and no-load power there are startup power threshold registers (e.g. pstartth(35h)). refer to 6.4 configuration and calibration registers . the power threshold registers are defined for all-phase-sum active , reactive and apparent power. the m90e36a starts metering when the corresponding all-phase-sum powe r is greater than the startup threshold. when the power value is lower than the startup threshold, energy is not accumulated and it is assumed as in no-load status. refer to figure-5 . there are also no-load current threshold registers for active , reactive and apparent energy metering participation for each of the 3 phases. if |p|+|q| is lowe r than the corresponding powe r threshold, that particul ar phase will not be accumu- lated. refer to the pstartth register and other threshold registers. there are also no-load status bits (the tpnoload/tqnoload bits (b14~15, enstatus0 )) defined to reflect the no-load status. the m90e36a does not output any pulse in no-load st atus. the power-on state is of no-load status. figure-5 metering startup handling 0 1 phase active power from dsp 0 phase active energy metering power threshold |p|+|q|> pphaseth? 0 1 0 0 1 phase reactive power from dsp 0 phase reactive energy metering power threshold |p|+|q|> qphaseth? 0 1 0 0 1 phase apparent power from dsp 0 phase apparent energy metering power threshold |p|+|q|> sphaseth? 0 1 0 total active energy metering + abs > pstartth? 0 1 0 total active power 3 phases total reactive energy metering + abs > qstartth? 0 1 0 total reactive power 3 phases total (arithmetic sum) apparent energy metering + abs > sstartth? 0 1 0 total apparent power 3 phases a/b/c a/b/c a/b/c
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 16 3.5 measurement function measured parameters can be divided to 7 types as follows: - active/ reactive/ apparent power - fundamental/ harmonic power - rms for voltage and current - power factor - phase angle - frequency - temperature measured parameters are average values that are averaged among 16 phase-voltage cycles (about 320ms at 50hz) except for the temperature. the measured parameter update frequency is approximately 3hz. refer to table-15 . 3.5.1 active/ reactive/ apparent power active/ reactive/ apparent power measurem ent registers can be divided as below: - active, reactive, apparent power - all-phase-sum / phase a / phase b / phase c - apparent power all-phase vector sum altogether there are 13 power registers. refer to 6.6.1 power and power factor registers and the svmeant register (98h). per-phase apparent power is defined as the produ ct of measured vrms and irms of that phase. all-phase-sum power is measured by ar ithmetically summing the per-phase measured power. the summing of phases can be configured by the mmode0 register. the ?apparent power all-phase vector sum? is done according to ieee std 1459. 3.5.2 fundamental / harmonic active power fundamental / harmonic active power measur ement registers can be divided as below: - fundamental and harmonic power - all-phase-sum / phase a / phase b / phase c altogether there are 8 power registers. refer to 6.6.2 fundamental/ harmonic power and voltage/ current rms registers . 3.5.3 mean power factor (pf) power factor is defined for those cases: a ll-phase-sum / phase a / phase b / phase c. altogether there are 4 power factor registers. refer to 6.6.1 power and power factor registers . for all-phase: the all-phase-sum apparent power selection is defin ed by the cf2esv bit (b6, mmode0 ). for each of the phase:: 3.5.4 voltage / current rms voltage/current rms registers can be divided as follows: per-phase: phase a / phase b / phase c voltage / current altogether there ar e 6 rms registers. neutral line current rms: ower apparent_p sum all_phase_ er active_pow sum all_phase_ = pf_all ower apparent_p er active_pow = pf_phase
17 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 neutral line current can be measured by a/d, or calculated by instantaneous value . altogether there are 2 n line current rms registers. refer to 6.6.2 fundamental/ harmonic power and voltage/ current rms registers . 3.5.5 phase angle phase angle measurement registers can be divided as below: - phase a / phase b / phase c - voltage / current altogether there are 6 phase angle registers. refer to 6.6.3 thd+n, frequency, angle and temperature registers . note: calculation of phase angle is based on zero-crossing in terval and frequency. there might be big error when voltage/ current at low value. 3.5.6 frequency frequency is measured using phase a voltage by default. when phase a has voltage sag, phase c is used, and phase b is used when both phase a and c have voltage sag. refer to 6.6.3 thd+n, frequency, angle and temperature registers . 3.5.7 temperature chip junction-temperature is measured roughly every 100 ms by on-chip temperature sensor. refer to 6.6.3 thd+n, frequency, angl e and temperature registers . 3.5.8 thd+n for voltage and current voltage thd+n is defined as: current thd+n's definition is similar to that of voltage. registers: - voltage and current - phase a / phase b / phase c altogether there are 6 thd+n registers. refer to 6.6.3 thd+n, frequency, angle and temperature registers . the thd+n measurement is mainly used to monitor the percen tage of harmonics in the system. accuracy is not guaran- teed when thd+n is lower than 10%. c b a n i i i i + + = ental rms_fundam ental rms_fundam rms_total v v - (v 2 2 )
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 18 3.6 fourier anal ysis function the m90e36a offers a hardware dft engine for 2 nd to 32 nd order harmonic component, both v and i of each phase with the same time period. the registers can be divided as follows: - voltage and current for each phase - phase a / phase b / phase c - 32 frequency components (fundamental value, and harmonic ratios) - total harmonic distortion (thd) the harmonic analysis is implemented wit h a dft engine. the dft period is 0.5 second, which gives a resolution fre- quency bin of 2hz. the input samples are multiplied with a ha nning window before feeding to the dft processor. the dft processor computes the fundamental and harmonic components based on the measured line frequency and sampling rate, which is 8khz. figure-6 analysis function hanning window x dft computation engine frequency components for fundamental and harmonic post- processing ratios for fundamental and harmonic harmonic analyzer line frequency sample frequency sample capture input sample from dsp processor x scaler to dma module
19 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 3.7 power mode the m90e36a has four power modes. the power mode is solely defined by the pm1 and pm0 pins. 3.7.1 normal mode (n mode) in normal mode, all function blocks are active except for current detec tor block. refer to figure-7 . figure-7 block diagram in normal mode table-2 power mode mapping pm1:pm0 value power mode 11 normal (n mode) 10 partial measurement (m mode) 01 detection (d mode) 00 idle (i mode) vdd18 regulator temperature sensor current detector adc-v1 adc-v2 adc-v3 adc-i1 adc-i2 adc-i3 adc-in spi interface dsp energy metering (forward/reverse active/reactive/cf generator) measure and monitoring (v/i/rms, sag, phase, freq) signal analyzer adc sample capture, thd control logic zero crossing cf out power on reset crystal oscillator dma reference voltage osci osco power mode configuration disabled irq warn out
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 20 3.7.2 idle mode (i mode) in idle mode, all functions are shut off. the analog blocks' power supply is powered but circuits are se t into power-down mode, i.e, power supply applied but all current paths are shut off. there is very low current sinc e only very low device leakage could exist in this mode. the digital i/os' supply is powered. in i/o and analog interfac e, the input signals from digital core (which is not powered) will be set to known state as described in ta b l e - 3 . the pm1 and pm0 pins which are controlled by external mcu are active and can configure the m90e36a to other modes. figure-8 block diagram in idle mode please note that since the digital i/o is not shut off, the i/o circuit is active in the idle mode. the application shall make sure that valid logic levels are applied to the i/o. ta b l e - 3 lists digital i/o and power pins? states in idle mode. it lis ts the requirements for inputs and the output level for out- put. for bi-directional pins, the direction is defined. vdd18 regulator temperature sensor current detector adc-v1 adc-v2 adc-v3 adc-i1 adc-i2 adc-i3 adc-in spi interface dsp energy metering (forward/reverse active/reactive/cf generator) measure and monitoring (v/i/rms,sag, phase, freq) signal analyzer adc sample capture, thd control logic zero crossing cf out power on reset crystal oscillator dma reference voltage osci osco power mode configuration disabled irq warn out
21 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 table-3 digital i/o and power pin states in idle mode name i/o type type pin state in idle mode reset i lvttl input level shall be vdd33. cs blvttl i/o set in input mode. input level shall be vdd33 or vss. sclk b lvttl i/o set in input mode. input level shall be vdd33 or vss. sdo b lvttl i/o set in input mode. input level shall be vdd33 or vss. sdi b lvttl i/o set in input mode. input level shall be vdd33 or vss. pm1 pm0 ilvttl as defined in ta b l e - 2 osci osco i o osc oscillator powered down. osco stays at fixed (low) level. zx0 zx1 zx2 olvttl0 cf1 cf2 cf3 cf4 olvttl0 warnout o lvttl 0 irq0 irq1 olvttl0 dma_ctrl i lvttl i/o set in input mode. input level shall be vdd33 or vss. vdd18 i power regulated 1.8v: high impedance dvdd i power digital power supply: powered by system avdd i power analog power supply: powered by system test i input always tie to ground in system application
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 22 3.7.3 detection mode (d mode) in detection mode, the current detector is active. the curr ent detector compares whether any phase current exceeds the configured threshold using low-power comparators. when the current of one phase or multiple phases exceeds the configured threshold, the m90e36a asserts the irq0 pin to high and hold it until power mode change. the irq0 st ate is cleared when entering or exiting detection mode. when the current of all three current channels exceed the conf igured threshold, the m90e36a asserts the irq1 pin to high and hold it until power mode change. the irq1 state is cleared when entering or exiting detection mode. the threshold registers need to be programmed in normal mode before entering detection mode. the digital i/o state is the same as that in idle state (except for irq0/irq1 and pm1/pm0). the m90e36a has two comparators for detecting each phase?s positive and negative current. each comparator?s thresh- old can be set individually. the two comparators are both acti ve by default, which called ?double-side detection?. user also can enable one comparator only to save power co nsumption, which called ?s ingle-side detection?. double-side detection has faster response and can detect ?hal f-wave? current. but it consumes nearly twice as much power as single-side detection. comparators can be power-down by configuring the detectctrl register. figure-9 block diagram in detection mode vdd18 regulator temperature sensor current detector adc-v1 adc-v2 adc-v3 adc-i1 adc-i2 adc-i3 adc-in spi interface dsp energy metering (forward/reverse active/reactive/cf generator) measure and monitoring (v/i/rms, sag, phase, freq) signal analyzer adc sample capture, thd control logic zero crossing cf out power on reset crystal oscillator dma reference voltage osci osco power mode configuration disabled irq warn out
23 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 3.7.4 partial measurement mode (m mode) in this mode, voltage adcs, neutral line adc and digital circuits are inactive. the m90e36a measures the cu rrent rms of one line cycle. when the measurement is done, the m90e36a asserts the ir q0 pin high until the partial measurement mode exits. in this mode, the user needs to program the related registers (including pga gain, channel gain, offset, etc.) to make the current rms measuremen t accurate. refer to 5.2 partial measurement mode calibration . please note that not all registers in this mode is accessible. only the partial measurement related registers (14h ~1dh) and some special registers (00h, 01h, 03h, 07h,0eh, 0fh) can be accessed. figure-10 block diagram in partial measurement mode vdd18 regulator temperature sensor current detector adc-v1 adc-v2 adc-v3 adc-i1 adc-i2 adc-i3 adc-in spi interface dsp energy metering (forward/reverse active/reactive/cf generator) measure and monitoring (v/i/rms, sag, phase, freq) signal analyzer adc sample capture, thd control logic zero crossing cf out power on reset crystal oscillator dma reference voltage osci osco power mode configuration disabled irq warn out
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 24 3.7.5 transition of power modes the above power modes are controlled by the pm0 and pm1 pins . in application, the pm0 and pm1 pins are connected to external mcu. the pm0 and pm1 pins have internal rc- filters. generally, the m90e36a stays in idle mode most of the time wh ile outage. it enters detection mode at a certain interval (for example 5s) as controlled by the mcu. it informs the mcu if the current exceeds the configured threshold. the mcu then commands the m90e36a to enter partial measurement mode at a certain interval (e.g. 60s) to read related current. after current reading, the m90e36a gets back to the idle mode. the measured current may be used to count energy according to some metering model (lik e current rms multiplying the rated voltage to compute the power). any power mode transition goes through the idle mode, as shown in figure-11 . figure-11 power mode transition normal mode idle mode detection mode partial measurement mode
25 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 3.8 event detection 3.8.1 zero-crossing detection zero-crossing detector detects the zero-cro ssing point of the fundamental component of voltage and current for each of the 3 phases. zero-crossing signal can be independently confi gured and output. refer to the definition of the zxconfig register. 3.8.2 sag detection usually in the application the sag threshold is set to be 78 % of the reference voltage. the m90e36a generates sag event when there are less than three 8khz samples (absolute value) greater than the sag threshol d during two continuous 11ms time-window. for the computation of sag threshold register value, refer to application note 46104. the sag event is captured by the sagwarn bit (b3, sysstatus0 ). if the corresponding irq enable bit the sagwnen bit (b3, funcen0 ) is set, irq can be generated. refer to figure-28 . 3.8.3 phase loss detection the phase loss detection detects if there is one or more ph ases? voltage is less than the phase-loss threshold voltage. the processing and handling is similar to sag detection, only the threshold is different. the threshold computation flow is also similar. the typical threshold setting could be 10% un or less. if any phase line is detected as in phase-loss mode, that phase?s zero-crossing detection function (both voltage and cur- rent) is disabled. 3.8.4 neutral line overcurrent detection 3.8.4.1 sampled n-line the neutral line measured rms is checked with the threshold defined in the inwarnth1 register. if the n line current is greater than the threshol d, the inov1 bit (b15, sysstatus1 ) is set. irq1 is generated if the corresponding enable bit (the inov1en bit (b15, funcen1 )) is set. 3.8.4.2 computed n-line the neutral line computed current (calculated) rms is checked with the threshold defined in the inwarnth0 register. if the n line current is greater than the threshold, the inov0 bit (b14, sysstatus1 ) bit is set. irq1 is generated if the correspond- ing enable bit the inov0en bit (b14, funcen1 ) is set. 3.8.5 phase sequence error detection the phase sequence is detected in two cases: 3p4w and 3p3w, which is defined by the 3p3w bit (b8, mmode0 ). 3p4w case: correct sequence: voltage/current zero-cross ing sequence: phase-a, phase-b and phase-c. 3p3w case: correct sequence: voltage/current zero-crossing between phase-a and phase-c is greater than 180 degree. if the above mentioned criteria are violated , it is assumed as a phase sequence error. 3.9 dc and current rms estimation the m90e36a has a module named ?pms? which can estimate current channel rms or current channel arithmetic average (dc component). the measurement type is defined in the pmconfig register. it can be used to estimate current rms in partial measurement mode. since the pms block only consume very small power, it can be also used to estimate current rms in normal mode. the pms module is turned on in both partial measurement mode and normal mode. the result is in different format and different scale for t he rms and average respectively. the rms result is unsigned; while current average is signed. refer to 6.3.2 partial measurement mode registers for associated register definition.
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 26 4 spi / dma interface 4.1 interface description the interface can work in two modes: slave (spi) mode and master mode, which is also named dma (direct memory access) mode. the interface mode is determined by the dma_ctrl pin as below: five pins are associated with the interface as below: ? sdi ? data pin, bi-directional. ? sdo ? data pin, bi-directional. ? sclk ? bi-directional pin. it is a clock output pin in master mode and clock input pin in slave mode. ? cs ? bi-directional chip select pin . it is an output pin in master mode and input pin in slave mode. ? dma_ctrl ? uni-directional input pin. the external device pull this pin high to control the interface work in master mode for data dumping in dma mode. figure-12 slave mode figure-13 master mode (pin_dir_sel=0) mode dma_ctrl description slave (spi) mode 0 the interface works as normal four-wire spi interface. master (dma) mode 1 the interface operates as a master and dumps data to the other devices. spi interface logic (as slave) miso mosi sck cs host controller in master mode sck gpio1 mosi miso sclk cs gpio2 dma_ctrl dma_ctrl=0 sdi sdo spi interface logic (as master) mosi miso sck cs dsp slave mode sck spiss mosi miso sdi sdo sclk cs dma_ctrl=1 dma_ctrl gpio
27 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 4.2 slave mode: spi interface the interface works in slave mode when the dma_ctrl pin is low as shown in figure-12 . 4.2.1 spi slave interface format in the spi mode, data on sdi is shifted into the chip on the rising edge of sclk while data on sdo is shifted out of the chip on the falling edge of sclk. refer to figure-14 and figure-15 below for the timing diagram. access type: the first bit on sdi defines the access type as below: address: fixed 15-bit, following the access type bits. the lower 10-bit is decoded as address; the higher 5 bits are ?don't care?. read/write data: fixed as 16 bits. read sequence: figure-14 read sequence write sequence: figure-15 write sequence instruction description instruction format read read from registers 1 write write to registers 0 cs sclk sdi sdo 10 1 2 3 4 5 6 7 8 9 111213141516171819202122 24 a3 a6 a5 a4 register address high impedance d15 don't care d0 16-bit data 23 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 25 26 a2 a1 a0 27 28 29 30 31 32 a8 x x x x x a7 a9 cs sclk sdi sdo 10 123456789 11121314151617181920212223 a3 a7 a6 a5 a4 16-bit data high impedance d0 d7 d6 d5 d4 d3 d2 d1 register address d15 24 d14 d13 d12 d11 d10 d9 d8 a0 a1 a2 25 26 27 28 29 30 31 32 a8 x x x x x a9
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 28 4.2.2 reliability enhancement feature the spi read/write transaction is cs -low defined. each transaction can only access one register. within each cs -low defined transaction: write: access occurs only when cs goes from low to high and there ar e exactly 32 sclk cycles received during cs low period. read: if sclk>=16 (full address received), data is read out from internal registers and gets to the sdo pin; and the lasts- pidata register is updated. the r/c regi sters can only be cleared after the lastspidata register is updated. 4.3 master mode: dma the interface is defined to connect with vari ous dsp processors for adc samples dumping. for dma configure please refer to dmactrl register definition in 6.2 special registers . the interface works in master mode when the dma_ctrl pin is pulled high by the external device. in master mode, regis- ters in m90e36a cannot be accessed. the dump transaction can be stopped by the exte rnal device via pulling the dma_ctrl pin to low at any time. figure-13 shows a connection between m90e36a and a dsp processor where m90e36a acts as the master. 4.3.1 dma burst transfer for adc sampling when the dma_ctrl pin changes from low to high, the vo ltage and current channel adc samples (after decimation and frequency compensation) are dumped out serially through the interface with sclk frequency defined by the clk_div[3:0] bits (b3~0, dmactrl ). when the m90e36a detects that the dma_ctrl pin is de-asser ted, it stops the dma transaction after the current sample has been sent. clock dividing ratio the sclk frequency of spi interface is de fined by the clk_div[3:0] bits (b3~0, dmactrl ) as the following equation: here f sys_clk means system?s oscillator frequency. interface direction in dma mode, the interface direction of sdi/sdo pins are normally defined as figure-13 . but the direction also can be swapped by configuring t he pin_dir_sel bit (b8, dmactrl ). adc channel selection internally, the m90e36a has 7 adc channels. the user can sele ct which channel?s samples to be dumped out via configur- ing the adc_ch_sel[15:9] bits (b15~9, dmactrl ). each bit of the 7-bit field adc_ch_sel enables the data dump ing for one adc channel. set ?1? to a bit enables the dump of the corresponding adc channel samples. clock modes four clock modes are defined in master mode according to the clk_drv bit (b4, dmactrl ) and clk_idle bit (b5, dmac- trl ) configuration as the following diagram shows. 2 + 2 * clk_div f = f sys_clk sclk
29 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 figure-16 clock mode0 (clk_drv=0, clk_id le=0) and mode1 (clk_drv=0, clk_idle=1) figure-17 clock mode2 (clk_drv=1, clk_id le=0) and mode3 (clk_drv=1, clk_idle=1) for mode0 and mode1 (clk_drv = 0), the first edge of sclk is used by the slave to sample the data. for mode2 and mode3 (clk_drv=1), the first edge of sc lk is used by the master to drive out the data. cs deactivation for rate adaptation since the bit rate may be higher than the equivalent bit rate of the samples (for example, for 24-bit non-frame mode, the equivalent bit-rate is sample_rate*6*24bps). to compensate for that, the cs signal is de-asserted to wait for the new sam- ples and be asserted again once the new sample arrives. there are at least 2 sclk clock periods for cs resume from de-asserted state to assert state depending on the clock divid- ing ratio and adc channel selection. during cs de-asserted state, the sclk stays in idle state as configured by the clk_idle bit (b5, dmactrl ). data frame format and sample sequence in dma mode the m90e36a sends the adc samples (in 8k sample rate) contin uously in dma mode. the samples of all enabled adc channels are sent out in in terleaved manner, with the sequen ce of i4, i1, v1, i2, v2, and i3, v3 (if any channel is disabled, remove it from the list wh ile maintaining the sequence of the other channels). figure-18 shows an example of the sample sequence when the adc_ch_sel[1 5:9] bits (b15~9, dmactrl ) are configured to be ?0101001?. clock cycle # sclk (clk_idle=0) sclk (clk_idle=1) sdi/sdo cs 1234 n-2 n n-1 clock cycle # sclk (clk_idle=0) sclk (clk_idle=1) sdi/sdo cs 1234 n-2 n n-1
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 30 figure-18 sample sequence example bit sequence the samples sent over the interfaces are the processed data according to the ch_b itwidth[7:6] bits (b7~6, dmactrl ). all the samples sent are msb first. figure-19 shows an example of sample bit sequence for 32-bit sample bit width. figure-19 sample bit sequence example 4.3.2 control sequence for external device to start and stop the dma dump sequence, the external device follows the rules described below: ? start of the dump process: a) the external device configures the dmactrl register. b) the external device switches to spi sl ave mode. note that the parameters of cl ock idle state / driving edge, sample bit width and pin direction of spi_d0/spi_d1 configured to m90e36a should match with external device's settings. c) the external device asserts the dma_ctrl signal. the m90e36a swaps i/o direction if necessary after it has detected that master has asserted the dma. the samples are dumped out with a delay of at most 1 sample period (125us). ? stop of the dump process: a) the external device de-asserts the dma_ctrl signal. th e m90e36a stops the transaction after current (all selected) samples have been successfully sent out. b) the external device waits one sample period of 125us or detects that the cs signal is pulled hi gh, then switches the interface back to master mode. samples on mosi cs i1 i2 v3 i1 i2 v3 i1 i2 v3 samples 1 t=125s samples 2 samples n samples samples on mosi cs i1 i2 v3 b 23 b 16 b 15 b 8 b 7 b 0 0000 i1 sample n 8 pads 0000
31 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 5 calibration method 5.1 normal mode operation calibration calibration is done per phase and there is no need to calibrate for the all-phase-sum (total) parameters. the calibration method is as follows: step-1: register configuration for calibration - start to configure the system configurat ion registers by writing 5678h to the configstart register. - the m90e36a automatically reset the config uration registers to their default value. - program all the system configuration registers. - calculate and write the checksum to the cs0 register. - write 8765h to the configstart register (enable checksum checking). - system may check the warnout pin to see if there is a checksum error. the start register and checksum handling scheme is the same throughout the calibration process, so the following section does not describe the star t and checksum operation. step-2: measurement calibration (per-phase) - first calibrate offset at i = 0, u = 0 for current or/and voltage; ? configure calculated channel gain (the user needs to program the pga gain and dpga gain properly in order to get the calculated gain within 0 to 2 in step-1). ? read irms/ urms value. ? calculate the compensation value. ? write the calculated value to the offset register. - then calibrate gain at i = in (ib), u = un for current and voltage; ? read irms/ urms value. ? calculate the compensation value. ? write the calculated value to the gain register. step-3: metering calibration (per phase) - first calibrate the power/ energy offset. ? u = un, i = 0. ? read full 32 bits (or lower 16 bi ts) active and reactive power ? calculate the compensation values ? write the calculated values to the offset registers respectively. - then calibrate energy gain at unity power factor: ? pf=1.0, u = un, i = in (ib). ? connect cf1 to the calibration bench; ? user/ pc calculate the energy gain accordin g to the data got from calibration bench ? write the calculated value to the energy gain register. - then calibrate the phase angle compensation at 0.5 inductive power factor. ? pf=0.5l, u = un, i = in (ib), rated frequency = 50hz, or 60hz according to the application; ? cf1 connected to the calibration bench; ? user/ pc calculate the phase angle accordin g to the data got fr om calibration bench; ? write the calculated value to the phase angle register. 5.2 partial measurem ent mode calibration the calibration met hod is as follows: step-1: set the input current to zero and measure the current mean value (set measuretype = 1, write 1 to the remeasure bit (b14, pmconfig ) to trigger the measurement. refer to the pmirmsa register). negate the result register (the pmirmsa / pmirmsb / pmirmsc registers) reading (16-bit) and then write the result to the offset register. step-2: the output of partial measurement result = adc_input_ voltage *pga_gain*dpga_gain*65536 / 1.2. for instance, a 150 mvrms signal (from ct) with pga = 1 gets 8192 in the rms result register. step-3: the user needs to do its own conversion to get meaningf ul result. the scaling factor in user's software could be calibrated device per device.
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 32 6register 6.1 register list table-4 register list register address register name read/ write type functional description comment page status and special register 00h softreset w software reset p40 01h sysstatus0 r/c system status 0 p41 02h sysstatus1 r/c system status 1 p41 03h funcen0 r/w function enable 0 p43 04h funcen1 r/w function enable 1 p43 07h zxconfig r/w zero-crossing configuration config uration of zx0/ 1/2 pins? source p45 08h sagth r/w voltage sag threshold p45 09h phaselossth r/w voltage phase losing threshold similar to voltage sag threshold reg- ister p45 0ah inwarnth0 r/w threshold for calculated (ia + ib +ic) n line rms current check sysstatus0/1 register. p46 0bh inwarnth1 r/w threshold for sampled (from adc) n line rms current check sysstatus0/1 register. p46 0ch thdnuth r/w voltage thd warning threshol d check sysstatus0/1 register. p46 0dh thdnith r/w current thd warning threshold check sysstatus0/1 register. p46 0eh dmactrl r/w dma mode interface contro l dma mode interface control p47 0fh lastspidata r last read/ write spi value refer to 4.2.2 reliability enhance- ment feature p48 low power mode register 10h detectctrl r/w current detect control p49 11h detectth1 r/w channel 1 current threshold in detection mode p50 12h detectth2 r/w channel 2 current threshold in detection mode p50 13h detectth3 r/w channel 3 current threshold in detection mode p51 14h pmoffseta r/w ioffset for phase a in partial measure- ment mode p52 15h pmoffsetb r/w ioffset for phase b in partial measure- ment mode p52 16h pmoffsetc r/w ioffset for phase c in partial measure- ment mode p52 17h pmpga r/w pgagain configuration in partial mea- surement mode p52 18h pmirmsa r irms for phase a in partial measure- ment mode p52 19h pmirmsb r irms for phase b in partial measure- ment mode p53 1ah pmirmsc r irms for phase c in partial measure- ment mode p53
33 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 1bh pmconfig r/w measure configuration in partial mea- surement mode p53 1ch pmavgsamples r/w number of 8k samples to be averaged in rms/mean computation p53 1dh pmirmslsb r lsb bits of pmrrms[a/b/c] it returns msb of the mean measure- ment data in mean value test p54 configuration registers 30h configstart r/w calibration start command p56 31h plconsth r/w high word of pl_constant p57 32h plconstl r/w low word of pl_constant p57 33h mmode0 r/w metering method configuration p58 34h mmode1 r/w pga gain configuration p59 35h pstartth r/w active startup power threshold. refer to ta b l e - 5 . 36h qstartth r/w reactive startup power threshold. 37h sstartth r/w apparent startup power threshold. 38h pphaseth r/w startup power threshold (active e nergy accumulation) 39h qphaseth r/w startup power threshold (reactive e nergy accumulation) 3ah sphaseth r/w startup power threshold (apparent e nergy accumulation) 3bh cs0 r/w checksum 0 p60 calibration registers 40h calstart r/w calibration start command refer to ta b l e - 6 . 41h poffseta r/w phase a active power offset p61 42h qoffseta r/w phase a reactive power offset p61 43h poffsetb r/w phase b active power offset 44h qoffsetb r/w phase b reactive power offset 45h poffsetc r/w phase c active power offset 46h qoffsetc r/w phase c reactive power offset 47h gaina r/w phase a calibration gain p62 48h phia r/w phase a calibration phase angle p62 49h gainb r/w phase b calibration gain 4ah phib r/w phase b calibration phase angle 4bh gainc r/w phase c calibration gain 4ch phic r/w phase c calibration phase angle 4dh cs1 r/w checksum 1 table-4 register list (continued) register address register name read/ write type functional description comment page
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 34 fundamental/ harmonic ener gy calibration registers 50h harmstart r/w harmonic calibration startup com- mand refer to ta b l e - 7 . 51h poffsetaf r/w phase a fundamental active power offset 52h poffsetbf r/w phase b fundamental active power offset 53h poffsetcf r/w phase c fundamental active power offset 54h pgainaf r/w phase a fundamental active power gain 55h pgainbf r/w phase b fundamental active power gain 56h pgaincf r/w phase c fundamental active power gain 57h cs2 r/w checksum 2 measurement calibration 60h adjstart r/w measurement calibration startup command refer to ta b l e - 8 . 61h ugaina r/w phase a voltage rms gain 62h igaina r/w phase a current rms gain 63h uoffseta r/w phase a voltage rms offset 64h ioffseta r/w phase a current rms offset 65h ugainb r/w phase b voltage rms gain 66h igainb r/w phase b current rms gain 67h uoffsetb r/w phase b voltage rms offset 68h ioffsetb r/w phase b current rms offset 69h ugainc r/w phase c voltage rms gain 6ah igainc r/w phase c current rms gain 6bh uoffsetc r/w phase c voltage rms offset 6ch ioffsetc r/w phase c current rms offset 6dh igainn r/w sampled n line current rms gain 6eh ioffsetn r/w sampled n line current rms offset 6fh cs3 r/w checksum 3 table-4 register list (continued) register address register name read/ write type functional description comment page
35 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 energy register 80h apenergyt r/c total forward active energy refer to ta b l e - 9 . 81h apenergya r/c phase a forward active energy 82h apenergyb r/c phase b forward active energy 83h apenergyc r/c phase c forward active energy 84h anenergyt r/c total reverse active energy 85h anenergya r/c phase a reverse active energy 86h anenergyb r/c phase b reverse active energy 87h anenergyc r/c phase c reverse active energy 88h rpenergyt r/c total forward reactive energy 89h rpenergya r/c phase a forward reactive energy 8ah rpenergyb r/c phase b forward reactive energy 8bh rpenergyc r/c phase c forward reactive energy 8ch rnenergyt r/c total reverse reactive energy 8dh rnenergya r/c phase a reverse reactive energy 8eh rnenergyb r/c phase b reverse reactive energy 8fh rnenergyc r/c phase c reverse reactive energy 90h saenergyt r/c total (arithmetic sum) apparent e nergy 91h senergya r/c phase a apparent energy 92h senergyb r/c phase b apparent energy 93h senergyc r/c phase c apparent energy 94h svenergyt r/c (vector sum) total apparent energy 95h enstatus0 r metering status 0 p66 96h enstatus1 r metering status 1 p66 98h svmeant r (vector sum) total apparent power 99h svmeantlsb r lsb of (vector sum) total apparent power table-4 register list (continued) register address register name read/ write type functional description comment page
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 36 fundamental / harmonic energy register a0h apenergytf r/c total forward active fundamental e nergy refer to table-10 . p67 a1h apenergyaf r/c phase a forward active fundamental energy a2h apenergybf r/c phase b forward active fundamental energy a3h apenergycf r/c phase c forward active fundamental energy a4h anenergytf r/c total reverse active fundamental e nergy a5h anenergyaf r/c phase a reverse active fundamental energy a6h anenergybf r/c phase b reverse active fundamental energy a7h anenergycf r/c phase c reverse active fundamental energy a8h apenergyth r/c total forw ard active harmonic energy a9h apenergyah r/c phase a forward active harmonic e nergy aah apenergybh r/c phase b forward active harmonic e nergy abh apenergych r/c phase c forward active harmonic e nergy ach anenergyth r/c total reverse active harmonic energy adh anenergyah r/c phase a reverse active harmonic e nergy aeh anenergybh r/c phase b reverse active harmonic e nergy afh anenergych r/c phase c reverse active harmonic e nergy table-4 register list (continued) register address register name read/ write type functional description comment page
37 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 power and power factor registers b0h pmeant r total (all-pha se-sum) active power refer to ta b l e - 11 . p68 b1h pmeana r phase a active power b2h pmeanb r phase b active power b3h pmeanc r phase c active power b4h qmeant r total (all-phase-sum) reactive power b5h qmeana r phase a reactive power b6h qmeanb r phase b reactive power b7h qmeanc r phase c reactive power b8h sameant r total (arithmetic sum) apparent power b9h smeana r phase a apparent power bah smeanb r phase b apparent power bbh smeanc r phase c apparent power bch pfmeant r total power factor bdh pfmeana r phase a power factor beh pfmeanb r phase b power factor bfh pfmeanc r phase c power factor c0h pmeantlsb r lower word of total (all-phase-sum) active power c1h pmeanalsb r lower word of phase a active power c2h pmeanblsb r lower word of phase b active power c3h pmeanclsb r lower word of phase c active power c4h qmeantlsb r lower word of total (all-phase-sum) reactive power c5h qmeanalsb r lower word of phase a reactive power c6h qmeanblsb r lower word of phase b reactive power c7h qmeanclsb r lower word of phase c reactive power c8h sameantlsb r lower word of total (arithmetic sum) apparent power c9h smeanalsb r lower word of phase a apparent power cah smeanblsb r lower word of phase b apparent power cbh smeanclsb r lower word of phase c apparent power table-4 register list (continued) register address register name read/ write type functional description comment page
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 38 fundamental / harmonic power and vo ltage / current rms registers d0h pmeantf r total active fundamental power refer to table-12 . p69 d1h pmeanaf r phase a active fundamental power d2h pmeanbf r phase b active fundamental power d3h pmeancf r phase c active fundamental power d4h pmeanth r total active harmonic power d5h pmeanah r phase a active harmonic power d6h pmeanbh r phase b active harmonic power d7h pmeanch r phase c active harmonic power d8h irmsn1 r n line sampled current rms d9h urmsa r phase a voltage rms dah urmsb r phase b voltage rms dbh urmsc r phase c voltage rms dch irmsn0 r n line calculated current rms ddh irmsa r phase a current rms deh irmsb r phase b current rms dfh irmsc r phase c current rms e0h pmeantflsb r lower word of total active fundamen- tal power e1h pmeanaflsb r lower word of phase a active funda- mental power e2h pmeanbflsb r lower word of phase b active funda- mental power e3h pmeancflsb r lower word of phase c active funda- mental power e4h pmeanthlsb r lower word of total active harmonic power e5h pmeanahlsb r lower word of phase a active har- monic power e6h pmeanbhlsb r lower word of phase b active har- monic power e7h pmeanchlsb r lower word of phase c active har- monic power e9h urmsalsb r lower word of phase a voltage rms eah urmsblsb r lower word of phase b voltage rms ebh urmsclsb r lower word of phase c voltage rms edh irmsalsb r lower word of phase a current rms eeh irmsblsb r lower word of phase b current rms efh irmsclsb r lower word of phase c current rms table-4 register list (continued) register address register name read/ write type functional description comment page
39 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 thd+n, frequency, angle and temperature registers f1h thdnua r phase a voltage thd+n refer to table-13 . p70 f2h thdnub r phase b voltage thd+n f3h thdnuc r phase c voltage thd+n f5h thdnia r phase a current thd+n f6h thdnib r phase b current thd+n f7h thdnic r phase c current thd+n f8h freq r frequency f9h panglea r phase a mean phase angle fah pangleb r phase b mean phase angle fbh panglec r phase c mean phase angle fch temp r measured temperature fdh uanglea r phase a voltage phase angle feh uangleb r phase b voltage phase angle ffh uanglec r phase c voltage phase angle harmonic fourier analysis registers 100h ~ 1bfh r refer to table-14 . p71 1d0h ~ 1d1h r/w table-4 register list (continued) register address register name read/ write type functional description comment page
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 40 6.2 special registers 6.2.1 soft reset register softreset software reset 6.2.2 irq and warnout signal generation status bits in the sysstatus0 register generate an interrupt and get the irq0 pin to be asserted if the corresponding enable bits are set in the funcen0 register. status bits in the sysstatus1 register generate an interrupt and get the irq1 pin to be asserted, if the corresponding enable bits are set in the funcen1 register. some of the status signals can also assert the warnout pin. the following diagram illustrates how the status bits, enable bits and irq/ warnout pins work together. figure-20 irq and warnout generation address: 00h type: write default value: 0000h bit name description 15 - 0 softre- set[15:0] software reset register. the m90e36a resets only if 789a h is written to this register. the reset domain is the same as the reset pin or power on reset. reading th is register always return 0. status 1 status 2 status n enable 2 enable n register bits in sysstatus0/1 register bits in funcen0/1 irq0/1 warnout event capture event capture en status without enable status with enable read clear read clear read clear read clear read clear read clear
41 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 sysstatus0 system status 0 address: 01h type: read/clear default value: 0000h bit name description 15 - reserved. * 14 cs0err this bit indicates cs0 (3bh) checksum status. 0: cs0 checksum co rrect (default) 1: cs0 checksum error. the warnout pi n is asserted at the same time. 13 - reserved. 12 cs1err this bit indicates cs1 (4dh) checksum status. 0: cs1 checksum co rrect (default) 1: cs1 checksum error. the warnout pi n is asserted at the same time. 11 - reserved. 10 cs2err this bit indicates cs2 (57h) checksum status. 0: cs2 checksum co rrect (default) 1: cs2 checksum error. the warnout pi n is asserted at the same time. 9- reserved. 8cs3err this bit indicates cs3 (6fh) checksum status. 0: cs3 checksum co rrect (default) 1: cs3 checksum error. the warnout pi n is asserted at the same time. 7 urevwn this bit indicates whether there is any error with the voltage phase sequence. 0: no error with the voltage phase sequence (default) 1: error with the voltage phase sequence. 6 irevwn this bit indicates whether there is any error with the current phase sequence. 0: no error with the current phase sequence (default) 1: error with the current phase sequence. 5 - 4 - reserved. 3sagwarn this bit indicates whether there is any voltage sag (voltage lower than threshold) in one phase or more. 0: no voltage sag (default) 1: voltage sag. 2 phasel- osewn this bit indicates whether there is any voltage phase losing in one phase or more. 0: no voltage phase losing (default) 1: voltage phase losing. 1-0 - reserved. note: all reserved bits of any register should be ig nored when reading and should be written with zero.
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 42 sysstatus1 system status 1 address: 02h type: read/clear default value: 0000h bit name description 15 inov1 this bit indicates whether the n line current sampli ng value is greater than the threshold set by the inwarnth1 register. 0: not greater than the threshold (default) 1: greater than the threshold. 14 inov0 this bit indicates whether the calculated n line current is greater than t he threshold set by the inwarnth0 register. 0: not greater than the threshold (default) 1: greater than the threshold. 13-12 - reserved. 11 thduov this bit indicates whether one or more voltage thdux (thdua/ thdub/ thduc) is greater than the threshold set by the thdnuth register. 0: not greater than the threshold (default) 1: greater than the threshold. 10 thdiov this bit indicates whether one or more current thdix (thdia/ thdib/ thdic) is greater than the thresh- old set by the thdnith register. 0: not greater than the threshold (default) 1: greater than the threshold. 9dftdone this bit indicates whether the dft data is ready. 0: not ready (default) 1: ready. 8- reserved. 7 revqchgt when there is any direction change of active/reactiv e energy for all-phase-sum or individual phase (from forward to reverse, or from reverse to forward), th e corresponding status bit is set. the judgment of direc- tion change is solely based on the energy register (not related to the cf pulses), and dependent on the energy register resolution (0.01cf / 0. 1cf setting set by the 001lsb bit (b9, mmode0 )). 0: direction of active/react ive energy no change (default) 1: direction of active/reactive energy changed the status bits are revqchgt/ revpchgt are status bits for all-phase-sum and revqchga/ revqchgb/ revqchgc/ revpchga/ revpchgb/ revp chgc are for individual phase. 6revqchga 5revqchgb 4revqchgc 3 revpchgt 2 revpchga 1 revpchgb 0 revpchgc
43 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 funcen0 function enable 0 address: 03h type: read/write default value: 0000h bit name description 15-11 - reserved. 10 cs2erren this bit determines whether to enable th e interrupt when the cs2err bit (b10, sysstatus0 ) is set. 0: disable (default) 1: enable 9-8 - reserved. 7 urevwnen this bit determines whether to enable th e interrupt when the urevwn bit (b7, sysstatus0 ) is set. 0: disable (default) 1: enable 6 irevwnen this bit determines whether to enable th e interrupt when the irevwn bit (b6, sysstatus0 ) is set. 0: disable (default) 1: enable 5-4 - reserved. 3sagwnen this bit determines whether to enable the volt age sag interrupt when the sagwarn bit (b3, sysstatus0 ) is set. 0: disable (default) 1: enable 2 phasel- osewnen this bit determines whether to enable the interrupt when the phaselosewn bit (b2, sysstatus0 ) is set. 0: disable (default) 1: enable 1-0 - reserved.
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 44 funcen1 function enable 1 address: 04h type: read/write default value: 0000h bit name description 15 inov1en this bit determines whether to enable th e interrupt when the inov1 bit (b15, sysstatus1 ) is set. 0: disable (default) 1: enable 14 inov0en this bit determines whether to enable th e interrupt when the inov0 bit (b14, sysstatus1 ) is set. 0: disable (default) 1: enable 13-12 - reserved. 11 thduoven this bit determines whether to enable th e interrupt when the thduov bit (b11, sysstatus1 ) is set. 0: disable (default) 1: enable 10 thdioven this bit determines whether to enable th e interrupt when the thdiov bit (b10, sysstatus1 ) is set. 0: disable (default) 1: enable 9dftdone this bit determines whether to enable th e interrupt when the dftdone bit (b9, sysstatus1 ) is set. 0: disable (default) 1: enable 8- reserved. 7revqchgten these bits determine whether to enable the correspondi ng interrupt when any of the direction change bits (b7~b0, sysstatus1 ) is set. 0: disable (default) 1: enable 6 revqchgaen 5 revqchgben 4 revqchgcen 3 revpchgten 2 revpchgaen 1 revpchgben 0 revpchgcen
45 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 6.2.3 special configuration registers zxconfig zero-crossing configuration sagth voltage sag threshold phaselossth voltage phase losing threshold address: 07h type: read/write default value: 0001h bit name description 15:13 zx2src[2:0] these bits select the signal source for the zx2, zx1 or zx0 pins. 12:10 zx1src[2:0] 9:7 zx0src[2:0] 6:5 zx2con[1:0] these bits configure zero-cro ssing mode for the zx2, zx1 and zx0 pins. 4:3 zx1con[1:0] 2:1 zx0con[1:0] 0zxdis this bit determines whether to disable the zx signals: 0: enable 1: disable all the zx signals to ?0? (default). address: 08h type: read/write default value: 0000h bit name description 15:0 sagth unsigned 16-bit integer with unit related to pga and voltage sense circuits. refer to 3.8.2 sag detection. address: 09h type: read/write default value: 0000h bit name description 15:0 phaselossth unsigned 16-bit integer with unit related to pga and voltage sense circuits. refer to 3.8.3 phase loss detection. code source 011 fixed-0 000 ua 001 ub 010 uc 111 fixed-0 100 ia 101 ib 110 ic code zero-crossing configuration 00 positive zero-crossing 01 negative zero-crossing 10 all zero-crossing 11 no zero-crossing output
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 46 inwarnth0 neutral current (calculated) warning threshold inwarnth1 neutral current (sampled) warning threshold thdnuth voltage thd warning threshold thdnith current thd warning threshold address: 0ah type: read/write default value: ffffh bit name description 15:0 inwarnth0 neutral current (calculated) warning threshold. threshold for calculated (ia + ib +ic) n line rms current. unsigned 16 bit, unit 1ma. if n line rms current is greater than the threshold, the inov0 bit (b14, sysstatus1) will be asserted if enabled. refer to 3.8.4.2 computed n-line. address: 0bh type: read/write default value: ffffh bit name description 15:0 inwarnth1 neutral current (sampled) warning threshold. threshold for sampled (from adc) n line rms current. unsigned 16 bit, unit 1ma. if n line rms current is greater than the threshold, the inov1 bit (b15, sysstatus1) will be asserted if enabled. refer to 3.8.4.1 sampled n-line. address: 0ch type: read/write default value: ffffh bit name description 15:0 thdnuth voltage thd warning threshold. voltage thd+n threshold. unsigned 16 bit, unit 0.01%. exceeding the threshold will assert the thduov bit (b11, sysstatus1) if enabled. address: 0dh type: read/write default value: ffffh bit name description 15:0 thdnith current thd warning threshold. current thd+n threshold. unsigned 16-bit, unit 0.01%. exceeding the threshold will assert the thdiov bit (b10, sysstatus1) if enabled.
47 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 dmactrl dma mode interface control address: 0eh type: read/write default value: 7e44h bit name description 15:9 adc_ch_se l these bits configure the data source of the adc channel. each bit enables the data dumping for one adc channel as the following diagram shows. set a ?1? to a bit enables the dumping of the corresponding adc channel samples. note: i1 to phase a and i3 to phase c mapping can be swapped by configuring the i1i3swap bit (b13, mmode0) . 8 pin_dir_se l this bit configures the direction of the sdi and sdo pins. 7:6 ch_bit_wid th these bits configure the bit width for each channel. 5clk_idle this bit configures the idle state clock level. 0: idle low (default) 1: idle high 4 clk_drv this bit configures which edge to drive data out. 0: second edge drives data out. (default) 1: first edge drives data out. 3:0 clk_div divide ratio to generate sclk frequency from sys_clk. default value is ?100?. b15 b14 b13 b12 b11 b10 b9 i4 v1 i1 v2 i2 v3 i3 pin_dir_sel master mode (dma_ctrl=1) 0 sdi mosi sdo miso 1 sdi miso sdo mosi code channel bit width 00 32 bits 01 24 bits (default) 10 16 bits 11 reserved
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 48 6.2.4 last spi data register lastspidata last read/write spi value address: 0fh type: read default value: 0000h bit name description 15:0 lastspidata1 5 - lastspidata0 this register is a special register which logs data of the previous spi read or write access especially for read/clear registers. this register is useful when the user wants to ch eck the integrity of the last spi access.
49 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 6.3 low-power modes registers 6.3.1 detection mode registers current detection register latching scheme is: when any of the 4 current detection regi sters (0x10 - 0x13) were programmed, all the 4 current detection registers (includ- ing the registers that not being programmed) will be automatically latched into the current detector's internal configuration latches at the same time. those latched configuration values are not subject to digital reset signals and will be kept in all the 4 power modes. the power up value of those latches is no t deterministic, so user need s to program the current detec- tion registers to update. figure-21 current detection register latching scheme detectctrl current detect control address: 10h type: read/write default value: 0000h bit name description 15:6 - reserved. 5:0 detectctrl detector power-down, active high: [5:3]: power-down for negative detector of channel 3/2/1; [2:0]: power-down for positiv e detector of channel 3/2/1. 0x10 0x11 0x12 0x13 latch latch latch latch current detector register write update registers current detector block
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 50 detectth1 channel 1 current threshold in detection mode detectth2 channel 2 current threshold in detection mode address: 11h type: read/write default value: 0000h bit name description 15 - reserved. 14:8 calcoden channel 1 current negative detector calculation code. code mapping: 7'b000-0000, vc=-4.28mv=-3.03mvrms (vc is the threshold of low power computation) 7'b111-1111, vc=12.91mv=9.14mvrms dac typical resolution is [12.91-(-4.28)]/127=135.4 v=95.7 vrms 7 - reserved. 6:0 calcodep channel 1 current positive detector calculation code. code mapping: 7'b000-0000, vc=-4.28mv=-3.03mvrms (vc is the threshold of low power computation) 7'b111-1111, vc=12.91mv=9.14mvrms dac typical resolution is [12.91-(-4.28)]/127=135.4 v=95.7 vrms address: 12h type: read/write default value: 0000h bit name description 15 - reserved. 14:8 calcoden channel 2 current negative detector calculation code. code mapping: 7'b000-0000, vc=-4.28mv=-3.03mvrms (vc is the threshold of low power computation) 7'b111-1111, vc=12.91mv=9.14mvrms dac typical resolution is [12.91-(-4.28)]/127=135.4 v=95.7 vrms 7 - reserved. 6:0 calcodep channel 2 current positive detector calculation code. code mapping: 7'b000-0000, vc=-4.28mv=-3.03mvrms (vc is the threshold of low power computation) 7'b111-1111, vc=12.91mv=9.14mvrms dac typical resolution is [12.91-(-4.28)]/127=135.4 v=95.7 vrms
51 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 detectth3 channel 3 current threshold in detection mode the calibration method is that, the user program the detecti on threshold and test with the standard input signal until the output trips. address: 13h type: read/write default value: 0000h bit name description 15 - reserved. 14:8 calcoden channel 3 current negative detector calculation code. code mapping: 7'b000-0000, vc=-4.28mv=-3.03mvrms (vc is the threshold of low power computation) 7'b111-1111, vc=12.91mv=9.14mvrms dac typical resolution is [12.91-(-4.28)]/127=135.4 v=95.7 vrms 7 - reserved. 6:0 calcodep channel 3 current positive detector calculation code. code mapping: 7'b000-0000, vc=-4.28mv=-3.03mvrms (vc is the threshold of low power computation) 7'b111-1111, vc=12.91mv=9.14mvrms dac typical resolution is [12.91-(-4.28)]/127=135.4 v=95.7 vrms
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 52 6.3.2 partial measurement mode registers pmoffseta ioffset for phase a in partial measurement mode pmoffsetb ioffset for phase b in partial measurement mode pmoffsetc ioffset for phase c in partial measurement mode pmpga pgagain configuration in partial measurement mode pmirmsa irms for phase a in pa rtial measurement mode address: 14h type: read/write default value: 0000h bit name description 15-14 - reserved. 13:0 pmoffseta phase a current offset in partial measurement mode. address: 15h type: read/write default value: 0000h bit name description 15-14 - reserved. 13:0 pmoffsetb phase b current offset in partial measurement mode. address: 16h type: read/write default value: 0000h bit name description 15-14 - reserved. 13:0 pmoffsetc phase c current offset in partial measurement mode. address: 17h type: read/write default value: 0000h bit name description 15-14 dpga dpga in partial measurement mode. 13:0 pgagain pgagain in partial measurement mode refer to the mmode1 register for encoding and mapping. address: 18h type: read default value: 0000h bit name description 15:0 pmirmsa * current rms/mean result in partial measurement mode. format: it is unsigned for rm s while signed for mean value. note: for current measuring in partial measurement mode, current gain is suggested to realized by external mcu and current rms value shall not exceed 40a.
53 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 pmirmsb irms for phase b in pa rtial measurement mode pmirmsc irms for phase c in pa rtial measurement mode pmconfig measure configuration in partial measurement mode pmavgsamples number of 8k samples to be averaged address: 19h type: read default value: 0000h bit name description 15:0 pmirmsb * current rms/mean result in partial measurement mode. format: it is unsigned for rm s while signed for mean value. note: for current measuring in partial measurement mode, current gain is suggested to realized by external mcu and current rms value shall not exceed 40a. address: 1ah type: read default value: 0000h bit name description 15:0 pmirmsc * current rms/mean result in partial measurement mode. format: it is unsigned for rm s while signed for mean value. note: for current measuring in partial measurement mode, current gain is suggested to realized by external mcu and current rms value shall not exceed 40a. address: 1bh type: read/write default value: 0000h bit name description 15 - reserved. 14 remeasure this bit is ?1?-write-only. write ?1? to this bit will trigger another measurement cycle. 13 measure- startzx this bit configures start of measurement whether starts from zero crossing point. 0: measurement start immediately (default) 1: measurement start from zero-crossing point 12 measuretype this bit indicates the measurement type. 0: rms measurement (default) 1: mean value (dc average) measurement 11-1 - reserved. 0pmbusy this bit indicates the measure status. this bit is read-only. 0: measurement done (default) 1: measurement in progress address: 1ch type: read default value: 00a0h bit name description 15:0 - number of 8k samples to be averaged in rms/mean computation.
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 54 pmirmslsb lsb bits of pmrrms[a/b/c] address: 1dh type: read default value: 0000h bit name description 15:12 - reserved. 11:8 irmsclsb these bits indicate lsb of the corresponding phase rms measurement result if the measuretype bit (b12, pmconfig ) =0. these bits indicate msb of the corresponding phase mean measurement result if the measuretype bit (b12, pmconfig ) =1. 7:4 irmsblsb 3:0 irmsalsb
55 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 6.4 configuration and ca libration registers 6.4.1 start registers and associated checksum operation scheme the start registers ( configstart (30h), calstart (40h), harmstart (50h) and adjstart (60h)) and associated registers / checksum have a special operation scheme to protect important configuration data, illustrated below in the diagram. start registers have multiple valid settings for different operation modes. figure-22 start and checksum register operation scheme start register value usage operation 6886h power up state it is the value after reset. this state blocks checksum checking error generation 5678h calibration similar like 6886h, this state blocks checksum checking error generatio n. writing with this value trigger a reset to the associated registers. 8765h operation checksum checking is enabled and if error detected, irq/warn is asserted and metering stopped. other error force checksum error generation and system stop. xxxstart register start associated regisers checksum (computed) checksum computation 0 1 irq/warnout generation metering enable 0 1 checksum error error xxxstart = 5678h xxxstart = 8765h 0 1 checksum (programmed) compare error? user write user read ? xxxstart refers to configstart, calstart, harmstart and adjstart. those registers and their assoicated checksum computation has similar behavior. ? xxxstart registers reset value is 6886h. ? writing 5678h to xxxstart register will trigger a reset to its associated register. register can be accessed after reset. ? xxxstart associated register is the register between xxxstart and associated checksum 0 1 xxxstart = 6886h 0
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 56 6.4.2 configuration registers configstart configure start command table-5 configuration registers register address register name read/write type functional description power-on value and comments configuration registers * 30h configstart r/w calibration start command 6886h 31h plconsth r/w high word of pl_constant 0861h 32h plconstl r/w low word of pl_constant c468h 33h mmode0 r/w hpf/integrator on/off, cf and all-phase energy computation configuration 0087h 34h mmode1 r/w pga gain configuration 0000h 35h pstartth r/w active startup power threshold. 16 bit unsigned integer, unit: 0.00032 watt 0000h. 36h qstartth r/w reactive startup power threshold. 16 bit unsigned integer, unit: 0.00032 var 0000h 37h sstartth r/w apparent startup power threshold. 16 bit unsigned integer, unit: 0.00032 va 0000h 38h pphaseth r/w startup power threshold (for |p|+|q| of a phase) for any phase participating active e nergy accumulation. common for phase a/ b/c. 0000h 16 bit unsigned integer, unit: 0.00032 watt/var 39h qphaseth r/w startup power threshold (for |p|+|q| of a phase) for any phase participating reac- tive energy accumulation. common for phase a/b/c. 0000h 16bit unsigned integer, unit: 0.00032 watt/var 3ah sphaseth rw startup power threshold (for |p|+|q| of a phase) for any phase participating appar- ent energy accumulation. common for phase a/b/c. 0000h 16 bit unsigned integer, unit: 0.00032 watt/var 3bh cs0 r/w checksum 0 checksum register. 421ch (calculated value after reset) note: for details, please refer to application note 46104. address: 30h type: read/write default value: 6886h bit name description 15 - 0 calstart[15:0] refer to 6.4.1 start registers and associ ated checksum operation scheme .
57 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 plconsth high word of pl_constant plconstl low word of pl_constant address: 31h type: read/write default value: 0861h bit name description 15 - 0 plcon- sth[15:0] the plconsth[15:0] and plconstl[15:0] bits are high word and low word of pl_constant respectively. pl_constant is a constant which is proportional to the sampling ratios of voltage and current, and inversely proportional to the meter constant. pl_const ant is a threshold for energy calculated inside the chip, i.e., energy larger than pl_constant will be accumulated as 0.01cfx in the corresponding energy registers and then output on cfx if one cf reaches. it is suggested to set pl_constant as a multiple of 4 so as to double or redouble meter constant in low current state to save verification time. address: 32h type: read/write default value: c468h bit name description 15 - 0 plcon- stl[15:0] the plconsth[15:0] and plconstl[15:0] bits are high word and low word of pl_constant respectively. it is suggested to set pl_constant as a multiple of 4.
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 58 mmode0 metering method configuration address: 33h type: read/write default value: 0087h bit name description 15-14 - reserved. 13 i1i3swap this bit defines phase mapping for i1 and i3: 0: i1 maps to phase a, i3 maps to phase c (default) 1: i1 maps to phase c, i3 maps to phase a note: i2 always maps to phase b. 12 freq60hz current grid operating line frequency. 0: 50hz (default) 1: 60hz 11 hpfoff disable hpf in the signal processing path. 10 didten enable integrator for didt current sensor. 0: disable (default) 1: enable 9 001lsb energy register lsb configuration for all energy registers: 0: 0.1cf (default) 1: 0.01cf 83p3w this bit defines the voltage/current phase sequence detection mode: 0: 3p4w (default) 1: 3p3w (ua is uab, uc is ucb, ub is not used) 7cf2varh cf2 pin source: 0: apparent energy 1: reactive energy (default) 6 cf2esv this bit is to configure the apparent energy type in power factor calibration, and in cf2 output if apparent energy is selected by setting cf2varh=0. 0:all-phase apparent energy arithmetic su m (default) 1:all-phase apparent energy vector sum 5 - reserved. 4 absenq these bits configure the calculation method of tota l (all-phase-sum) reactive/active energy and power: 0: arithmetic sum: (default) et=ea*enpa+ eb*enpb+ ec*enpc pt= pa*enpa+ pb*enpb+ pc*enpc 1: absolute sum: et=|ea|*enpa+ |eb|*enpb+ |ec|*enpc pt=|pa|*enpa+ |pb|*enpb+ |pc|*enpc note: et is the total (all-phase-sum) energy, ea/eb /ec are the signed phase a/b/c energy respectively. reverse energy is negative. pt is the total (all-p hase-sum) power, pa/pb/pc are the signed phase a/b/c power respectively. reverse power is negative. 3 absenp 2enpa these bits configure whether phase a/b/c are count ed into the all-phase sum energy/power (p/q/s). 1: corresponding phase a/b/c to be counted into the all-phase sum energy/power (p/q/s) (default) 0: corresponding phase a/b/c not counted into the all-phase sum energy/power (p/q/s) 1enpb 0enpc
59 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 mmode1 pga gain configuration address: 34h type: read/write default value: 0000h bit name description 15-14 dpga_gain digital pga gain for the 4 current channels. this gain is implemented at the e nd of decimation filter. 00: gain = 1 (default) 01: gain = 2 10: gain = 4 11: gain = 8 13-0 pga_gain pga gain for all adc channels. mapping: [13:12]: v3 [11:10]: v2 [9:8]: v1 [7:6]: i4 [5:4]: i3 [3:2]: i2 [1:0]: i1 encoding: 00: 1x (default) 01: 2x 10: 4x 11: n/a
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 60 cs0 checksum 0 there are multiple start register and checksum (cs0/cs1/cs2 /cs3) registers for different crucial register blocks. those registers are handled in the similar way. address: 3bh type: read/write default value: 421ch bit name description 15 - 0 cs0[15:0] this register should be written after the 31h-3ah regi sters are written. suppose the high byte and the low byte of the 31h-3ah registers are shown in the below table. the calculation of the cs0 register is as follows: the low byte of 3bh register is: l 3b =mod( h 31 + h 32 +...+ h 3a + l 31 + l 32 +...+ l 3a , 2^8) the high byte of 3bh register is: h 3b = h 31 xor h 32 xor... xor h 3a xor l 31 xor l 32 xor... xor l 3a the m90e36a calculates cs0 regularly. if the value of the cs0 register and the calculation by the m90e 36a is different when configstart =8765h, the cs0err bit (b14, sysstatus0 ) is set and the warnout and irq pins are asserted. note : the readout value of the cs0 register is the ca lculation by the m90e36a, which is different from what is written. register address high byte low byte 31h h 31 l 31 32h h 32 l 32 33h h 33 l 33 34h h 34 l 34 35h h 35 l 35 36h h 36 l 36 37h h 37 l 37 38h h 38 l 38 39h h 39 l 39 3ah h 3a l 3a
61 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 6.4.3 energy calibration registers poffseta phase a active power offset qoffseta phase a reactive power offset table-6 calibration registers register address register name read/write type functional description power-on value calibration registers 40h calstart r/w calibration start command 6886h 41h poffseta r/w phase a active power offset 0000h 42h qoffseta r/w phase a reactive power offset 0000h 43h poffsetb r/w phase b active power offset 0000h 44h qoffsetb r/w phase b reactive power offset 0000h 45h poffsetc r/w phase c active power offset 0000h 46h qoffsetc r/w phase c reactive power offset 0000h 47h gaina r/w phase a active/reactive energy cali- bration gain 0000h 48h phia r/w phase a calibration phase angle 0000h 49h gainb r/w phase b active/reactive energy cali- bration gain 0000h 4ah phib r/w phase b calibration phase angle 0000h 4bh gainc r/w phase c active/reactive energy cali- bration gain 0000h 4ch phic r/w phase c calibration phase angle 0000h 4dh cs1 * r/w checksum 1 0000h note: the calculation of the cs1 register is similar as the cs0 register by calculating the 41h-4ch registers. for details, please refer to application note 46104. address: 41h type: read/write default value: 0000h bit name description 15-0 offset power offset. signed 16-bit integer. address: 42h type: read/write default value: 0000h bit name description 15-0 offset power offset. signed 16-bit integer.
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 62 gaina phase a active/reactive energy calibration gain phia phase a calibration phase angle the phase b and phase c?s calibration registers are similar as phase a. address: 47h type: read/write default value: 0000h bit name description 15-0 gain energy calibration gain. signed integer. actual power gain = (1+ gain) address: 48h type: read/write default value: 0000h bit name description 15 delayv 0: delay cycles are applied to current channel. (default) 1: delay cycles are applied to voltage channel. 14:10 - reserved. 9:0 delaycycles unit is 2.048mhz cycle. it is an unsigned 10 bit integer.
63 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 6.4.4 fundamental/harmonic energy calibration registers table-7 fundamental/harmonic energy calibration registers register address register name read/write type functional description power-on value 50h harmstart r/w harmonic calibration startup com- mand 6886h 51h poffsetaf r/w phase a fundamental active power offset 0000h 52h poffsetbf r/w phase b fundamental active power offset 0000h 53h poffsetcf r/w phase c fundamental active power offset 0000h 54h pgainaf r/w phase a fundamental active power gain 0000h 55h pgainbf r/w phase b fundamental active power gain 0000h 56h pgaincf r/w phase c fundamental active power gain 0000h 57h cs2 * r/w checksum 2 0000h note: the calculation of the cs 2 register is similar as the cs0 register by calculating the 51h-56h registers. for details, please refer to application note 46104.
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 64 6.4.5 measurement calibration table-8 measurement calibration registers register address register name read/write type functional description power-on value 60h adjstart r/w measurement calibration startup command 6886h 61h ugaina r/w phase a voltage rms gain ce40h 62h igaina r/w phase a current rms gain 7530h 63h uoffseta r/w phase a voltage rms offset 0000h 64h ioffseta r/w phase a current rms offset 0000h 65h ugainb r/w phase b voltage rms gain ce40h 66h igainb r/w phase b current rms gain 7530h 67h uoffsetb r/w phase b voltage rms offset 0000h 68h ioffsetb r/w phase b current rms offset 0000h 69h ugainc r/w phase c voltage rms gain ce40h 6ah igainc r/w phase c current rms gain 7530h 6bh uoffsetc r/w phase c voltage rms offset 0000h 6ch ioffsetc r/w phase c current rms offset 0000h 6dh igainn r/w sampled n line current rms gain 7530h 6eh ioffsetn r/w sampled n line current rms offset 0000h 6fh cs3 * r/w checksum 3 8ebeh note: the calculation of the cs3 register is similar as the cs0 register by calculating the 61h-6eh registers.
65 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 6.5 energy register 6.5.1 regular energy registers table-9 regular energy registers register address register name read/write type functional description comment 80h apenergyt r/c total forward active energy resolution is 0.1cf/0.01cf. 0.01cf / 0.1cf setting is def ined by the 001lsb bit (b9, mmode0 ). cleared after read. 81h apenergya r/c phase a forward active energy 82h apenergyb r/c phase b forward active energy 83h apenergyc r/c phase c forward active energy 84h anenergyt r/c total reverse active energy 85h anenergya r/c phase a reverse active energy 86h anenergyb r/c phase b reverse active energy 87h anenergyc r/c phase c reverse active energy 88h rpenergyt r/c total forward reactive energy 89h rpenergya r/c phase a forward reactive energy 8ah rpenergyb r/c phase b forward reactive energy 8bh rpenergyc r/c phase c forward reactive energy 8ch rnenergyt r/c total reverse reactive energy 8dh rnenergya r/c phase a reverse reactive energy 8eh rnenergyb r/c phase b reverse reactive energy 8fh rnenergyc r/c phase c reverse reactive energy 90h saenergyt r/c total (arithmetic sum) apparent e nergy 91h senergya r/c phase a apparent energy 92h senergyb r/c phase b apparent energy 93h senergyc r/c phase c apparent energy 94h svenergyt r/c (vector sum) total apparent energy 95h enstatus0 r metering status 0 96h enstatus1 r metering status 1 98h svmeant r (vector sum) total apparent power complement, msb is always ?0?; xx.xxx kva 99h svmeantlsb r lsb of (vector sum) total apparent power lsb of svmeant. unit/lsb is 4/65536 va
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 66 enstatus0 metering status 0 enstatus1 metering status 1 address: 95h type: read default value: f000h bit name description 15 tqnoload all-phase-sum reactive power no-load condition detected. 14 tpnoload all-phase-sum active power no-load condition detected. 13 tasnoload all-phase-sum apparent power no-load condition detected. 12 tvsnoload all-phase-sum vectored sum appare nt active power no-load condition detected. 11-4 - reserved. 3 cf4revflag cf4/cf3/cf2/cf1 forward/reverse flag ? reflec t the direction of the current cf pulse. 0: forward (default) 1: reverse 2 cf3revflag 1 cf2revflag 0 cf1revflag address: 96h type: read default value: 0000h bit name description 15-7 - reserved. 6 sagphasea these bits indicate whether there is voltage sag on phase a, b or c respectively. 0: no voltage sag (default) 1: voltage sag 5 sagphaseb 4 sagphasec 3 - reserved. 2 phaselossa these bits indicate whether there is a phase loss in phase a/b/c. 0: no phase loss (default) 1: phase loss. 1 phaselossb 0 phaselossc
67 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 6.5.2 fundamental / harmonic energy register table-10 fundamental / harmonic energy register register address register name read/write type functional description comment a0h apenergytf r/c total forward active fundamental e nergy resolution is 0.1cf / 0.01cf. 0.01cf / 0.1cf setting is def ined by the 001lsb bit (b9, mmode0 ). cleared after read. a1h apenergyaf r/c phase a forward active fundamental energy a2h apenergybf r/c phase b forward active fundamental energy a3h apenergycf r/c phase c forward active fundamen- tal energy a4h anenergytf r/c total reverse active fundamental e nergy a5h anenergyaf r/c phase a reverse active fundamen- tal energy a6h anenergybf r/c phase b reverse active fundamen- tal energy a7h anenergycf r/c phase c reverse active fundamental energy a8h apenergyth r/c total forward active harmonic energy a9h apenergyah r/c phase a forward active harmonic e nergy aah apenergybh r/c phase b forward active harmonic e nergy abh apenergych r/c phase c forward active harmonic e nergy ach anenergyth r/c total reverse active harmonic energy adh anenergyah r/c phase a reverse active harmonic e nergy aeh anenergybh r/c phase b reverse active harmonic e nergy afh anenergych r/c phase c reverse active harmonic e nergy
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 68 6.6 measurement registers 6.6.1 power and power factor registers table-11 power and power factor register register address register name read/write type functional description comment b0h pmeant r total (all-phase-sum) active power complement, msb as the sign bit xx.xxx kw 1lsb corresponds to 1watt for phase a/ b/c, and 4watt for total (all-phase-sum) b1h pmeana r phase a active power b2h pmeanb r phase b active power b3h pmeanc r phase c active power b4h qmeant r total (all-phase-sum) reactive power complement, msb as the sign bit xx.xxx kvar 1lsb corresponds to 1var for phase a/ b/c, and 4var for total (all-phase-sum) b5h qmeana r phase a reactive power b6h qmeanb r phase b reactive power b7h qmeanc r phase c reactive power b8h sameant r total (arithmetic sum) apparent power complement, msb always '0' xx.xxx kva 1lsb corresponds to 1va for phase a/b/ c, and 4va for total (all-phase-sum) b9h smeana r phase a apparent power bah smeanb r phase b apparent power bbh smeanc r phase c apparent power bch pfmeant r total power factor signed, msb as the sign bit x.xxx lsb is 0.001. range from -1000 to +1000 bdh pfmeana r phase a power factor beh pfmeanb r phase b power factor bfh pfmeanc r phase c power factor c0h pmeantlsb r lower word of total (all-phase-sum) active power lower word of active powers. 1llsb * corresponds to 4/256 watt c1h pmeanalsb r lower word of phase a active power lower word of active powers. 1llsb corresponds to 1/256 watt c2h pmeanblsb r lower word of phase b active power c3h pmeanclsb r lower word of phase c active power c4h qmeantlsb r lower word of total (all-phase-sum) reactive power lower word of reactive powers. 1llsb corresponds to 4/256 var c5h qmeanalsb r lower word of phase a reactive power lower word of reactive powers. 1llsb corresponds to 1/256 var c6h qmeanblsb r lower word of phase b reactive power c7h qmeanclsb r lower word of phase c reactive power c8h sameantlsb r lower word of total (arithmetic sum) apparent power lower word of apparent powers. 1llsb corresponds to 4/256 va c9h smeanalsb r lower word of phase a apparent power lower word of apparent powers. 1llsb corresponds to 1/256 va cah smeanblsb r lower word of phase b apparent power cbh smeanclsb r lower word of phase c apparent power note: all the lower 8 bits of c0h-cbh registers and e0h-efh regi sters are always zero. only the higher 8 bits of these register s are valid. in this document, llsb means bit 8 of the lower registers as below: b15 b14 b13 b12 b11 b10 b9 b8 (llsb) b7 b6 b5 b4 b3 b2 b1 b0
69 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 6.6.2 fundamental/ harmonic power and voltage/ current rms registers table-12 fundamental/ harmonic power and voltage/ current rms registers register address register name read/write type functional description comment d0h pmeantf r total active fundamental power complement, 16-bit integer with unit of 4watt. 1lsb corresponds to 4watt d1h pmeanaf r phase a active fundamental power complement, 16-bit integer with unit of 1watt. 1lsb corresponds to 1watt d2h pmeanbf r phase b active fundamental power d3h pmeancf r phase c active fundamental power d4h pmeanth r total active harmonic power complement, 16-bit integer with unit of 4watt. 1lsb corresponds to 4watt d5h pmeanah r phase a active harmonic power complement, 16-bit integer with unit of 1watt. 1lsb corresponds to 1watt d6h pmeanbh r phase b active harmonic power d7h pmeanch r phase c active harmonic power d8h irmsn1 r n line sampled current rms unsigned 16-bit integer with unit of 0.001a 1lsb corresponds to 0.001 a d9h urmsa r phase a voltage rms 1lsb corresponds to 0.01 v dah urmsb r phase b voltage rms dbh urmsc r phase c voltage rms dch irmsn0 r n line calculated current rms unsigned 16-bit integer with unit of 0.001a 1lsb corresponds to 0.001 a ddh irmsa r phase a current rms deh irmsb r phase b current rms dfh irmsc r phase c current rms e0h pmeantflsb r lower word of total active fundamen- tal power lower word of d0h register. 1llsb * corresponds to 4/256 watt e1h pmeanaflsb r lower word of phase a active funda- mental power lower word of registers from d1h to d3h. 1llsb corresponds to 1/256 watt e2h pmeanbflsb r lower word of phase b active funda- mental power e3h pmeancflsb r lower word of phase c active funda- mental power e4h pmeanthlsb r lower word of total active harmonic power lower word of d4h register. 1llsb corresponds to 4/256 watt e5h pmeanahlsb r lower word of phase a active har- monic power lower word of registers from d5h to d7h. 1llsb corresponds to 1/256 watt e6h pmeanbhlsb r lower word of phase b active har- monic power e7h pmeanchlsb r lower word of phase c active har- monic power e9h urmsalsb r lower word of phase a voltage rms lower word of registers from d9h to dbh. 1llsb corresponds to 0.01/256v eah urmsblsb r lower word of phase b voltage rms ebh urmsclsb r lower word of phase c voltage rms edh irmsalsb r lower word of phase a current rms lower word of registers from ddh to dfh. 1llsb corresponds to 0.001/256a eeh irmsblsb r lower word of phase b current rms efh irmsclsb r lower word of phase c current rms
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 70 6.6.3 thd+n, frequency, angle and temperature registers note: all the lower 8 bits of c0h-cbh registers and e0h-efh regi sters are always zero. only the higher 8 bits of these register s are valid. in this document, llsb means bit 8 of the lower registers as below: table-13 thd+n, frequency, angle and temperature registers register address register name read/write type functional description comment f1h thdnua r phase a voltage thd+n 1lsb corresponds to 0.01% f2h thdnub r phase b voltage thd+n f3h thdnuc r phase c voltage thd+n f5h thdnia r phase a current thd+n 1lsb corresponds to 0.01% f6h thdnib r phase b current thd+n f7h thdnic r phase c current thd+n f8h freq r frequency 1lsb corresponds to 0.01 hz f9h panglea r phase a mean phase angle signed, msb as the sign bit 1lsb corresponds to 0.1-degree, -180.0~+180.0 fah pangleb r phase b mean phase angle fbh panglec r phase c mean phase angle fch temp r measured temperature 1lsb corresponds to 1 c signed, msb as the sign bit fdh uanglea r phase a voltage phase angle always ?0? feh uangleb r phase b voltage phase angle signed, msb as the sign bit take phase a voltage as base voltage 1lsb corresponds to 0.1 degree, -180.0~+180.0 ffh uanglec r phase c voltage phase angle table-12 fundamental/ harmonic power and voltage/ current rms registers (continued) register address register name read/write type functional description comment b15 b14 b13 b12 b11 b10 b9 b8 (llsb) b7 b6 b5 b4 b3 b2 b1 b0
71 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 6.7 harmonic fourier analysis registers table-14 harmonic fourier analysis results registers register address register name read/write type functional description comment 100h ai_hr2 r phase a, current, harmonic ratio for 2-th order component harmonic ratio (%) = register value / 163.84 101h ai_hr3 r phase a, current, harmonic ratio for 3-th order component 102h ai_hr4 r phase a, current, harmonic ratio for 4-th order component ? r 11eh ai_hr32 r phase a, current, harmonic ratio for 32-th order component 11fh ai_thd r phase a, current, total harmonic dis- tortion ratio 120h bi_hr2 r phase b, current, harmonic ratio for 2-th order component harmonic ratio (%) = register value / 163.84 121h bi_hr3 r phase b, current, harmonic ratio for 3-th order component 122h bi_hr4 r phase b, current, harmonic ratio for 4-th order component ? r 13eh bi_hr32 r phase b, current, harmonic ratio for 32-th order component 13fh bi_thd r phase b, current, total harmonic dis- tortion ratio 140h ci_hr2 r phase c, current, harmonic ratio for 2-th order component harmonic ratio (%) = register value / 163.84 141h ci_hr3 r phase c, current, harmonic ratio for 3-th order component 142h ci_hr4 r phase c, current, harmonic ratio for 4-th order component ? r 15eh ci_hr32 r phase c, current, harmonic ratio for 32-th order component 15fh ci_thd r phase c, current, total harmonic dis- tortion ratio 160h av_hr2 r phase a, voltage, harmonic ratio for 2-th order component harmonic ratio (%) = register value / 163.84 161h av_hr3 r phase a, voltage, harmonic ratio for 3-th order component 162h av_hr4 r phase a, voltage, harmonic ratio for 4-th order component ? r 17eh av_hr32 r phase a, voltage, harmonic ratio for 32-th order component 17fh av_thd r phase a, voltage, total harmonic dis- tortion ratio
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 72 180h bv_hr2 r phase b, voltage, harmonic ratio for 2-th order component harmonic ratio (%) = register value / 163.84 181h bv_hr3 r phase b, voltage, harmonic ratio for 3-th order component 182h bv_hr4 r phase b, voltage, harmonic ratio for 4-th order component ? r 19eh bv_hr32 r phase b, voltage, harmonic ratio for 32-th order component 19fh bv_thd r phase b, voltage, total harmonic dis- tortion ratio 1a0h cv_hr2 r phase c, voltage, harmonic ratio for 2-th order component harmonic ratio (%) = register value / 163.84 1a1h cv_hr3 r phase c, voltage, harmonic ratio for 3-th order component 1a2h cv_hr4 r phase c, voltage, harmonic ratio for 4-th order component ? r 1beh cv_hr32 r phase c, voltage, harmonic ratio for 32-th order component 1bfh cv_thd r phase c, voltage, total harmonic dis- tortion ratio 1c0h ai_fund r phase a, current, fundamental com- ponent value current, fundamental component value = register value * 3.2656*10 -3 / 2^scale, register (1c0h, 1c2h, 1c4h); voltage, fundamental component value = register value * 3.2656*10 -2 / 2^scale, register (1c1h, 1c3h, 1c5h). the scale is defined by the dft_scale (1d0h) register. 1c1h av_fund r phase a, voltage, fundamental com- ponent value 1c2h bi_fund r phase b, current, fundamental com- ponent value 1c3h bv_fund r phase b, voltage, fundamental com- ponent value 1c4h ci_fund r phase c, current, fundamental com- ponent value 1c5h cv_fund r phase c, voltage, fundamental com- ponent value 1d0h dft_scale rw input gain = 2^scale, i.e. scale = # of bit shifts [2:0]: scale for channel a-i. [5:3]: scale for channel b-i. [8:6]: scale for channel c-i. [10:9]: scale for channel a-v. [12:11]: scale for channel b-v. [14:13]: scale for channel c-v. [15]: window disable. ?1? disable the hanning window. input data is scaled before sampling or dft. 1d1h dft_ctrl rw bit[0]: dft_start. 0: reset and abort the dft computa- tion. 1: start the dft. this bit is automati- cally cleared after dft finishes. table-14 harmonic fourier analysis results registers register address register name read/write type functional description comment
73 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 7 electrical specification 7.1 electrical specification parameter min typ max unit test condition/ comments accuracy dc power supply rejection ratio (psrr) 0.1 % vdd=3.3v 0.3v, i=5a, v=220v, ct 1000:1, sampling resistor 4.8 ac power supply rejection ratio (psrr) 0.1 % vdd=3.3v superimposes 400mvrms, i=5a, v=220v, ct 1000:1, sampling resistor 4.8 active energy error (dynamic range 6000:1) 0.1 % ct 1000:1, sampling resistor 4.8 adc channel differential input voltage 0.12 0.07 0.04 720 360 180 mvrms pga=1 pga=2 pga=4 analog input pin absolute voltage range gnd-300 vdd- 1200 mv channel input impedance 120 80 50 k pga=1 pga=2 pga=4 channel sampling frequency 8 khz channel sampling bandwidth 2 khz temperature sensor and reference temperature sensor accuracy 1 c reference voltage 1.2 3.3 v, 25 c reference voltage temperature coefficient 6 15 ppm/c from -40 to 85 c current detectors current detector threshold range 2 3 4 mvrms 3.3 v, 25 c current detector threshold setting step/ resolu- tion 0.096 mvrms 3.3 v, 25 c current detector detection time (single-side) 32 ms current detector detection time (double-side) 17 ms crystal oscillator oscillator frequency ( f sys_clk ) 16.384 mhz the accuracy of crystal or external clock is 20 ppm, 10pf ~ 20pf crystal load capacitor integrated. power supply avdd 2.8 3.3 3.6 dvdd 2.8 3.3 3.6 vdd18 1.8 v operating currents normal mode operating current (i-normal) 23 ma 3.3 v, 25 c normal mode operating current with dft engine on (i-normal + dft) 23.5 ma 3.3 v, 25 c idle mode operating current (i-idle) 0.1 4 a detection mode operating current (i-detection) 180 100 250 140 a double-side detection (at 3.3 v, 25 c) single-side detection (at 3.3 v, 25 c)
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 74 partial measurement m ode operating current (i-measurement) 6.8 ma 3.3 v, 25c spi slave mode (spi) bit rate 100 1200k note 1 bps master mode (dma) bit rate 1800k bps esd machine model (mm) 400 v jesd22-a115 charged device model (cdm) 1000 v jesd22-c101 human body model (hbm) 6000 v jesd22-a114 latch up 100 ma jesd78a latch up 5.4 v jesd78a dc characteristics digital input high level (all digital pins except osci) 2.4 vdd v vdd=3.3v digital input low level (all digital pins except osci) 0.8 v vdd=3.3v digital input leakage current 1 a vdd=3.6v, vi=vdd or gnd digital output low level (cf1, cf2, cf3, cf4) 0.4 v vdd=3.3v, i ol =8ma digital output low level (irq0, irq1, warnout, zx0, zx1, zx2, sdo) 0.4 v vdd=3.3v, i ol =5ma digital output high level (cf1, cf2, cf3, cf4) 2.8 v vdd=3.3v, i oh =-8ma, by separately digital output high level (irq0, irq1, war- nout, zx0, zx1, zx2, sdo) 2.8 v vdd=3.3v, i oh =-5ma, by separately note 1: the maximum spi bit rate during current detector calibration is 900k bps. parameter min typ max unit test condition/ comments
75 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 7.2 metering/ measurement accuracy 7.2.1 metering accuracy metering accuracy or energy accuracy is calculated with relative error: where e mea is the energy measured by the meter, e real is the actual energy measured by a high accurate normative meter. energy type energy pulse adc range when gain=1 metering accuracy note active energy (per phase and all-phase-sum) cf1 pf=1.0 120 v-720mv 0.1% pf=0.5l, 180 v-720mv pf=0.8c, 150 v-720mv reactive energy (per phase and all-phase-sum) cf2 sin =1.0 120 v-720mv 0.2% sin =0.5l, 180 v-720mv sin =0.8c, 150 v-720mv apparent energy (per phase and arithmetic all-phase- sum) cf2 600 v-720mv note 2 0.2% apparent energy (vector sum) cf2 120 v-720mv 0.5% fundamental active energy (per phase and all-phase-sum) cf3 pf=1.0 120 v-720mv 0.2% pf=0.5l, 180 v-720mv pf=0.8c, 150 v-720mv harmonic active energy (per phase and all-phase-sum) cf4 pf=1.0 120 v-720mv 0.5% pf=0.5l, 180 v-720mv pf=0.8c, 150 v-720mv note 1: all the parameters in this ta ble is tested on atmel?s test platform. note 2: apparent energy is tested using ac tive energy with unity power factor since there?s no standard for apparent energy. si gnal below 600 v is not tested. % 100 ? = real real mea e e e
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 76 7.2.2 measurement accuracy the measurements are all calculated with fidu cial error except for frequency and thd. fiducial error is calculated as follows: where u mea means the measured data of one measurement parameter, and u real means the real/actual data of the parameter, u fv means the fiducial value of this measur ement parameter, which can be defined as table-15 . for the above mentioned parameters, the measurement accuracy requirement is 0.5% maximum. for frequency, temperature, thd+n, thd and harmonic analysis: parameter accuracy frequency: 0.01hz temperature: 1 c thd/harmonics: 5% relative error accuracy of all orders of harmonics: 5% relative error table-15 measurement parameter range and format measurement fiducial value (fv) m90e36a defined format range comment voltage reference voltage un xxx.xx 0 ~ 655.35v unsi gned integer with unit of 0.01v current maximum current imax (4in is recom- mended) xx.xxx 0 ~ 65.535a unsigned in teger with unit of 0.001a voltage rms un xxx.xx 0 ~ 65 5.35v unsigned in teger with un it of 0.01v current rms note 1 ib/in xx.xxx 0 ~ 65.535a unsigned integer with unit of 0.001a active/ reactive power note 1 un 4ib xx.xxx -32.768 ~ +32.767 kw/ kvar signed integer with unit/lsb of 1 watt/var apparent power un 4ib xx.xxx 0 ~ +32.767 kva unsigned integer with unit/lsb of 1 va frequency reference fre- quency 50 hz xx.xx 45.00~65.00 hz signed integer with unit/lsb of 0.01hz power factor 1.000 x.xxx -1.000 ~ +1.0 00 signed integer, lsb/unit = 0.001 phase angle note 2 180 o xxx.x -180 o ~ +180 o signed integer, unit/lsb = 0.1 o thd+n relative error is adopted, no fiducial value xx.xx 0.00%-99.99% unit is 0.01% thd 0.00%-399% arithmetic ratio, 2 bit integer and 14 bit fractional. harmonic component 0.00%-399% note 1: all registers are of 16-bit. for cases when the current or active/reactive/apparent power goes beyond the above range, it is su ggested to be handled by mcu in application. for example, register value can be calibrated to 1/2 of the actual value during calibratio n, then multiply 2 in application. note 2: phase angle is obtained when voltage/current crosses zero at the sampling frequency of 256khz. 100% * u u - u rror fiducial_e fv real mea =
77 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 harmonic component% = where means the measuring value of the h th harmonic voltage/current; means the given or actual value of the h th harmonic voltage/current. 100 i u i u i u hn hn h ? ) ( ) ( ) ( h i u ) ( hn i u ) (
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 78 7.3 interface timing 7.3.1 spi interface timing (slave mode) the spi interface timing is as shown in figure-23 and table-16 . figure-23 spi timing diagram table-16 spi timing specification symbol description min. typical max. unit t csh minimum cs high level time 2t note 1 +10 ns t css cs setup time 2t+10 ns t csd cs hold time 3t+10 ns t cld clock disable time 1t ns t cyc sclk cycle 7t+10 ns t clh clock high level time 5t+10 ns t cll clock low level time 2t+10 ns t dis data setup time 2t+10 ns t dih data hold time 1t+10 ns t dw minimum data width 3t+10 ns t pd output delay 2t+20 ns t df output disable time 2t+20 ns note: 1. t means system clock cycle. t=1/ f sys_clk cs sclk sdi sdo t csh t css high impedance high impedance t csd t clh t cll t dis t dih t pd t df valid input valid output t cld t dw t cyc
79 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 7.3.2 dma timing (master mode) the dma timing is as shown in figure-24 and table-17 . figure-24 dma timing diagram table-17 dma timing specification symbol description min. typical max. unit t pd output delay 50 ns sclk (clk_idle=0) sclk (clk_idle=1) sdi/sdo cs t pd
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 80 7.4 power on reset timing in most case, the power of m90e36a and mcu are both derive d from 220v power lines. to make sure m90e36a is reset and can work properly, mcu must force m90e36a into idle mode firstly and then into normal mode. in this operation, rese t is held to high in idle mode and de-asserted by delay t1 after idle-nor mal transition. refer to figure-25 . figure-25 power on reset timing (m90e36a and mcu are powered on simultaneously) figure-26 power on reset timing in normal & partial measurement mode table-18 power on reset specification symbol description min typ max unit v h power on trigger voltage 2.5 2.7 v t 0 duration forced in idle mode after power on 1 ms t 1 delay time after power on or exit idle mode 5 16 40 ms pm[1:0] idle mode normal mode dvdd mcu startup reset t 1 t 0 dvdd reset t 1 v h
81 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 7.5 zero-crossing timing figure-27 zero-crossing ti ming diagram (per phase) table-19 zero-crossing specification symbol description min typ max unit t zx high level width 5 ms t d delay time 0.2 0.5 ms zx (positive zero-crossing) zx (negative zero-crossing) zx (all zero-crossing) t zx t d v
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 82 7.6 voltage sag a nd phase loss timing figure-28 voltage sag and phase loss timing diagram time voltage + threshold - threshold irq (if enabled) 11ms window sag/phase loss condition found in two consecutive windows assert of voltage sag / phase loss
83 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 7.7 absolute maximum rating parameter maximum limit relative voltage between avdd and agnd -0.3v~3.7v relative voltage between dvdd and dgnd -0.3v~3.7v analog input voltage (i1p, i1n, i2p, i2n, i3p, i3n, i4p, i4n, v1p, v1n, v2p, v2n, v3p, v3n) -0.6v~avdd digital input voltage -0.3v~3.6v operating temperature range -40~85 c maximum junction temperature 150 c package type thermal resistance ja unit condition tqfp48 58.5 c/w no airflow
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 84 ordering information atmel ordering code package carrier temperature range atm90e36a-au-r tqfp48 tape&reel industry (-40 c to +85 c ) atm90e36a-au-y tqfp48 tray industry (-40 c to +85 c )
85 m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 package dimensions
m90e36a [datasheet] atmel-46004a-se-m90e36a-datasheet_052214 86 revision history doc. rev. date comments 46004a 05/22/2014 initial document release in atmel.
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